1 /*-
2 * Copyright (c) 2002-2004 M. Warner Losh.
3 * Copyright (c) 2000-2001 Jonathan Chen.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD: src/sys/dev/pccbb/pccbb_pci.c,v 1.15 2005/10/08 06:58:51 imp Exp $
28 */
29
30 /*-
31 * Copyright (c) 1998, 1999 and 2000
32 * HAYAKAWA Koichi. All rights reserved.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by HAYAKAWA Koichi.
45 * 4. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 /*
61 * Driver for PCI to CardBus Bridge chips
62 *
63 * References:
64 * TI Datasheets:
65 * http://www-s.ti.com/cgi-bin/sc/generic2.cgi?family=PCI+CARDBUS+CONTROLLERS
66 *
67 * Written by Jonathan Chen <jon@freebsd.org>
68 * The author would like to acknowledge:
69 * * HAYAKAWA Koichi: Author of the NetBSD code for the same thing
70 * * Warner Losh: Newbus/newcard guru and author of the pccard side of things
71 * * YAMAMOTO Shigeru: Author of another FreeBSD cardbus driver
72 * * David Cross: Author of the initial ugly hack for a specific cardbus card
73 */
74
75 #include <sys/param.h>
76 #include <sys/systm.h>
77 #include <sys/proc.h>
78 #include <sys/errno.h>
79 #include <sys/kernel.h>
80 #include <sys/lock.h>
81 #include <sys/malloc.h>
82 #include <sys/sysctl.h>
83 #include <sys/kthread.h>
84 #include <sys/bus.h>
85 #include <sys/rman.h>
86 #include <sys/module.h>
87
88 #include <bus/pci/pcireg.h>
89 #include <bus/pci/pcivar.h>
90 #include <machine/clock.h>
91
92 #include <bus/pccard/pccardreg.h>
93 #include <bus/pccard/pccardvar.h>
94
95 #include <dev/pccard/exca/excareg.h>
96 #include <dev/pccard/exca/excavar.h>
97
98 #include <dev/pccard/pccbb/pccbbreg.h>
99 #include <dev/pccard/pccbb/pccbbvar.h>
100
101 #include "power_if.h"
102 #include "card_if.h"
103 #include "pcib_if.h"
104
105 #define DPRINTF(x) do { if (cbb_debug) kprintf x; } while (0)
106 #define DEVPRINTF(x) do { if (cbb_debug) device_printf x; } while (0)
107
108 #define PCI_MASK_CONFIG(DEV,REG,MASK,SIZE) \
109 pci_write_config(DEV, REG, pci_read_config(DEV, REG, SIZE) MASK, SIZE)
110 #define PCI_MASK2_CONFIG(DEV,REG,MASK1,MASK2,SIZE) \
111 pci_write_config(DEV, REG, ( \
112 pci_read_config(DEV, REG, SIZE) MASK1) MASK2, SIZE)
113
114 static void cbb_chipinit(struct cbb_softc *sc);
115
116 static struct yenta_chipinfo {
117 uint32_t yc_id;
118 const char *yc_name;
119 int yc_chiptype;
120 } yc_chipsets[] = {
121 /* Texas Instruments chips */
122 {PCIC_ID_TI1031, "TI1031 PCI-PC Card Bridge", CB_TI113X},
123 {PCIC_ID_TI1130, "TI1130 PCI-CardBus Bridge", CB_TI113X},
124 {PCIC_ID_TI1131, "TI1131 PCI-CardBus Bridge", CB_TI113X},
125
126 {PCIC_ID_TI1210, "TI1210 PCI-CardBus Bridge", CB_TI12XX},
127 {PCIC_ID_TI1211, "TI1211 PCI-CardBus Bridge", CB_TI12XX},
128 {PCIC_ID_TI1220, "TI1220 PCI-CardBus Bridge", CB_TI12XX},
129 {PCIC_ID_TI1221, "TI1221 PCI-CardBus Bridge", CB_TI12XX},
130 {PCIC_ID_TI1225, "TI1225 PCI-CardBus Bridge", CB_TI12XX},
131 {PCIC_ID_TI1250, "TI1250 PCI-CardBus Bridge", CB_TI125X},
132 {PCIC_ID_TI1251, "TI1251 PCI-CardBus Bridge", CB_TI125X},
133 {PCIC_ID_TI1251B,"TI1251B PCI-CardBus Bridge",CB_TI125X},
134 {PCIC_ID_TI1260, "TI1260 PCI-CardBus Bridge", CB_TI12XX},
135 {PCIC_ID_TI1260B,"TI1260B PCI-CardBus Bridge",CB_TI12XX},
136 {PCIC_ID_TI1410, "TI1410 PCI-CardBus Bridge", CB_TI12XX},
137 {PCIC_ID_TI1420, "TI1420 PCI-CardBus Bridge", CB_TI12XX},
138 {PCIC_ID_TI1421, "TI1421 PCI-CardBus Bridge", CB_TI12XX},
139 {PCIC_ID_TI1450, "TI1450 PCI-CardBus Bridge", CB_TI125X}, /*SIC!*/
140 {PCIC_ID_TI1451, "TI1451 PCI-CardBus Bridge", CB_TI12XX},
141 {PCIC_ID_TI1510, "TI1510 PCI-CardBus Bridge", CB_TI12XX},
142 {PCIC_ID_TI1520, "TI1520 PCI-CardBus Bridge", CB_TI12XX},
143 {PCIC_ID_TI4410, "TI4410 PCI-CardBus Bridge", CB_TI12XX},
144 {PCIC_ID_TI4450, "TI4450 PCI-CardBus Bridge", CB_TI12XX},
145 {PCIC_ID_TI4451, "TI4451 PCI-CardBus Bridge", CB_TI12XX},
146 {PCIC_ID_TI4510, "TI4510 PCI-CardBus Bridge", CB_TI12XX},
147 {PCIC_ID_TI6411, "TI6411 PCI-CardBus Bridge", CB_TI12XX},
148 {PCIC_ID_TI6420, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
149 {PCIC_ID_TI6420SC, "TI6420 PCI-CardBus Bridge", CB_TI12XX},
150 {PCIC_ID_TI7410, "TI7410 PCI-CardBus Bridge", CB_TI12XX},
151 {PCIC_ID_TI7510, "TI7510 PCI-CardBus Bridge", CB_TI12XX},
152 {PCIC_ID_TI7610, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
153 {PCIC_ID_TI7610M, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
154 {PCIC_ID_TI7610SD, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
155 {PCIC_ID_TI7610MS, "TI7610 PCI-CardBus Bridge", CB_TI12XX},
156
157 /* ENE */
158 {PCIC_ID_ENE_CB710, "ENE CB710 PCI-CardBus Bridge", CB_TI12XX},
159 {PCIC_ID_ENE_CB720, "ENE CB720 PCI-CardBus Bridge", CB_TI12XX},
160 {PCIC_ID_ENE_CB1211, "ENE CB1211 PCI-CardBus Bridge", CB_TI12XX},
161 {PCIC_ID_ENE_CB1225, "ENE CB1225 PCI-CardBus Bridge", CB_TI12XX},
162 {PCIC_ID_ENE_CB1410, "ENE CB1410 PCI-CardBus Bridge", CB_TI12XX},
163 {PCIC_ID_ENE_CB1420, "ENE CB1420 PCI-CardBus Bridge", CB_TI12XX},
164
165 /* Ricoh chips */
166 {PCIC_ID_RICOH_RL5C465, "RF5C465 PCI-CardBus Bridge", CB_RF5C46X},
167 {PCIC_ID_RICOH_RL5C466, "RF5C466 PCI-CardBus Bridge", CB_RF5C46X},
168 {PCIC_ID_RICOH_RL5C475, "RF5C475 PCI-CardBus Bridge", CB_RF5C47X},
169 {PCIC_ID_RICOH_RL5C476, "RF5C476 PCI-CardBus Bridge", CB_RF5C47X},
170 {PCIC_ID_RICOH_RL5C477, "RF5C477 PCI-CardBus Bridge", CB_RF5C47X},
171 {PCIC_ID_RICOH_RL5C478, "RF5C478 PCI-CardBus Bridge", CB_RF5C47X},
172
173 /* Toshiba products */
174 {PCIC_ID_TOPIC95, "ToPIC95 PCI-CardBus Bridge", CB_TOPIC95},
175 {PCIC_ID_TOPIC95B, "ToPIC95B PCI-CardBus Bridge", CB_TOPIC95},
176 {PCIC_ID_TOPIC97, "ToPIC97 PCI-CardBus Bridge", CB_TOPIC97},
177 {PCIC_ID_TOPIC100, "ToPIC100 PCI-CardBus Bridge", CB_TOPIC97},
178
179 /* Cirrus Logic */
180 {PCIC_ID_CLPD6832, "CLPD6832 PCI-CardBus Bridge", CB_CIRRUS},
181 {PCIC_ID_CLPD6833, "CLPD6833 PCI-CardBus Bridge", CB_CIRRUS},
182 {PCIC_ID_CLPD6834, "CLPD6834 PCI-CardBus Bridge", CB_CIRRUS},
183
184 /* 02Micro */
185 {PCIC_ID_OZ6832, "O2Micro OZ6832/6833 PCI-CardBus Bridge", CB_O2MICRO},
186 {PCIC_ID_OZ6860, "O2Micro OZ6836/6860 PCI-CardBus Bridge", CB_O2MICRO},
187 {PCIC_ID_OZ6872, "O2Micro OZ6812/6872 PCI-CardBus Bridge", CB_O2MICRO},
188 {PCIC_ID_OZ6912, "O2Micro OZ6912/6972 PCI-CardBus Bridge", CB_O2MICRO},
189 {PCIC_ID_OZ6922, "O2Micro OZ6922 PCI-CardBus Bridge", CB_O2MICRO},
190 {PCIC_ID_OZ6933, "O2Micro OZ6933 PCI-CardBus Bridge", CB_O2MICRO},
191 {PCIC_ID_OZ711E1, "O2Micro OZ711E1 PCI-CardBus Bridge", CB_O2MICRO},
192 {PCIC_ID_OZ711EC1, "O2Micro OZ711EC1/M1 PCI-CardBus Bridge", CB_O2MICRO},
193 {PCIC_ID_OZ711E2, "O2Micro OZ711E2 PCI-CardBus Bridge", CB_O2MICRO},
194 {PCIC_ID_OZ711M1, "O2Micro OZ711M1 PCI-CardBus Bridge", CB_O2MICRO},
195 {PCIC_ID_OZ711M2, "O2Micro OZ711M2 PCI-CardBus Bridge", CB_O2MICRO},
196 {PCIC_ID_OZ711M3, "O2Micro OZ711M3 PCI-CardBus Bridge", CB_O2MICRO},
197
198 /* SMC */
199 {PCIC_ID_SMC_34C90, "SMC 34C90 PCI-CardBus Bridge", CB_CIRRUS},
200
201 /* sentinel */
202 {0 /* null id */, "unknown", CB_UNKNOWN},
203 };
204
205 /************************************************************************/
206 /* Probe/Attach */
207 /************************************************************************/
208
209 static int
cbb_chipset(uint32_t pci_id,const char ** namep)210 cbb_chipset(uint32_t pci_id, const char **namep)
211 {
212 struct yenta_chipinfo *ycp;
213
214 for (ycp = yc_chipsets; ycp->yc_id != 0 && pci_id != ycp->yc_id; ++ycp)
215 continue;
216 if (namep != NULL)
217 *namep = ycp->yc_name;
218 return (ycp->yc_chiptype);
219 }
220
221 static int
cbb_pci_probe(device_t brdev)222 cbb_pci_probe(device_t brdev)
223 {
224 const char *name;
225 uint8_t progif, subclass, class;
226
227 /*
228 * Do we know that we support the chipset? If so, then we
229 * accept the device.
230 */
231 if (cbb_chipset(pci_get_devid(brdev), &name) != CB_UNKNOWN) {
232 device_set_desc(brdev, name);
233 return (0);
234 }
235
236 /*
237 * We do support generic CardBus bridges. All that we've seen
238 * to date have progif 0 (the Yenta spec, and successors mandate
239 * this).
240 */
241 class = pci_get_class(brdev);
242 subclass = pci_get_subclass(brdev);
243 progif = pci_get_progif(brdev);
244 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_CARDBUS &&
245 progif == 0) {
246 device_set_desc(brdev, "PCI-CardBus Bridge");
247 return (0);
248 }
249 return (ENXIO);
250 }
251
252 /*
253 * Still need this because the pci code only does power for type 0
254 * header devices.
255 */
256 static void
cbb_powerstate_d0(device_t dev)257 cbb_powerstate_d0(device_t dev)
258 {
259 u_int32_t membase, irq;
260
261 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
262 /* Save important PCI config data. */
263 membase = pci_read_config(dev, CBBR_SOCKBASE, 4);
264 irq = pci_read_config(dev, PCIR_INTLINE, 4);
265
266 /* Reset the power state. */
267 device_printf(dev, "chip is in D%d power mode "
268 "-- setting to D0\n", pci_get_powerstate(dev));
269
270 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
271
272 /* Restore PCI config data. */
273 pci_write_config(dev, CBBR_SOCKBASE, membase, 4);
274 pci_write_config(dev, PCIR_INTLINE, irq, 4);
275 }
276 }
277
278 /*
279 * Print out the config space
280 */
281 static void
cbb_print_config(device_t dev)282 cbb_print_config(device_t dev)
283 {
284 int i;
285
286 device_printf(dev, "PCI Configuration space:");
287 for (i = 0; i < 256; i += 4) {
288 if (i % 16 == 0)
289 kprintf("\n 0x%02x: ", i);
290 kprintf("0x%08x ", pci_read_config(dev, i, 4));
291 }
292 kprintf("\n");
293 }
294
295 static int
cbb_pci_attach(device_t brdev)296 cbb_pci_attach(device_t brdev)
297 {
298 static int curr_bus_number = 2; /* XXX EVILE BAD (see below) */
299
300 struct cbb_softc *sc = device_get_softc(brdev);
301 int rid, pribus;
302 device_t parent;
303
304 parent = device_get_parent(brdev);
305
306 sc->chipset = cbb_chipset(pci_get_devid(brdev), NULL);
307 sc->dev = brdev;
308 sc->cbdev = NULL;
309 sc->exca[0].pccarddev = NULL;
310 sc->domain = pci_get_domain(brdev);
311 sc->secbus = pci_read_config(brdev, PCIR_SECBUS_2, 1);
312 sc->subbus = pci_read_config(brdev, PCIR_SUBBUS_2, 1);
313 sc->pribus = pcib_get_bus(parent);
314 SLIST_INIT(&sc->rl);
315 cbb_powerstate_d0(brdev);
316
317 rid = CBBR_SOCKBASE;
318 sc->base_res = bus_alloc_resource_any(brdev, SYS_RES_MEMORY, &rid,
319 RF_ACTIVE);
320 if (!sc->base_res) {
321 device_printf(brdev, "Could not grab register memory\n");
322 return (ENOMEM);
323 } else {
324 DEVPRINTF((brdev, "Found memory at %08lx\n",
325 rman_get_start(sc->base_res)));
326 }
327
328 sc->bst = rman_get_bustag(sc->base_res);
329 sc->bsh = rman_get_bushandle(sc->base_res);
330 exca_init(&sc->exca[0], brdev, sc->bst, sc->bsh, CBB_EXCA_OFFSET);
331 sc->exca[0].flags |= EXCA_HAS_MEMREG_WIN;
332 sc->exca[0].chipset = EXCA_CARDBUS;
333 sc->chipinit = cbb_chipinit;
334 sc->chipinit(sc);
335
336 /*
337 * This is a gross hack. We should be scanning the entire pci
338 * tree, assigning bus numbers in a way such that we (1) can
339 * reserve 1 extra bus just in case and (2) all sub busses
340 * are in an appropriate range.
341 */
342 DEVPRINTF((brdev, "Secondary bus is %d\n", sc->secbus));
343 pribus = pci_read_config(brdev, PCIR_PRIBUS_2, 1);
344 if (sc->secbus == 0 || sc->pribus != pribus) {
345 if (curr_bus_number <= sc->pribus)
346 curr_bus_number = sc->pribus + 1;
347 if (pribus != sc->pribus) {
348 DEVPRINTF((brdev, "Setting primary bus to %d\n",
349 sc->pribus));
350 pci_write_config(brdev, PCIR_PRIBUS_2, sc->pribus, 1);
351 }
352 sc->secbus = curr_bus_number++;
353 sc->subbus = curr_bus_number++;
354 DEVPRINTF((brdev, "Secondary bus set to %d subbus %d\n",
355 sc->secbus, sc->subbus));
356 pci_write_config(brdev, PCIR_SECBUS_2, sc->secbus, 1);
357 pci_write_config(brdev, PCIR_SUBBUS_2, sc->subbus, 1);
358 }
359
360 /* attach children */
361 sc->cbdev = device_add_child(brdev, "cardbus", -1);
362 if (sc->cbdev == NULL)
363 DEVPRINTF((brdev, "WARNING: cannot add cardbus bus.\n"));
364 else if (device_probe_and_attach(sc->cbdev) != 0)
365 DEVPRINTF((brdev, "WARNING: cannot attach cardbus bus!\n"));
366
367 sc->exca[0].pccarddev = device_add_child(brdev, "pccard", -1);
368 if (sc->exca[0].pccarddev == NULL)
369 DEVPRINTF((brdev, "WARNING: cannot add pccard bus.\n"));
370 else if (device_probe_and_attach(sc->exca[0].pccarddev) != 0)
371 DEVPRINTF((brdev, "WARNING: cannot attach pccard bus.\n"));
372
373 /* Map and establish the interrupt. */
374 rid = 0;
375 sc->irq_res = bus_alloc_resource_any(brdev, SYS_RES_IRQ, &rid,
376 RF_SHAREABLE | RF_ACTIVE);
377 if (sc->irq_res == NULL) {
378 kprintf("cbb: Unable to map IRQ...\n");
379 goto err;
380 }
381
382 if (bus_setup_intr(brdev, sc->irq_res, INTR_MPSAFE, cbb_intr, sc,
383 &sc->intrhand, NULL)) {
384 device_printf(brdev, "couldn't establish interrupt");
385 goto err;
386 }
387
388 /* reset 16-bit pcmcia bus */
389 exca_clrb(&sc->exca[0], EXCA_INTR, EXCA_INTR_RESET);
390
391 /* turn off power */
392 cbb_power(brdev, CARD_OFF);
393
394 /* CSC Interrupt: Card detect interrupt on */
395 cbb_setb(sc, CBB_SOCKET_MASK, CBB_SOCKET_MASK_CD);
396
397 /* reset interrupt */
398 cbb_set(sc, CBB_SOCKET_EVENT, cbb_get(sc, CBB_SOCKET_EVENT));
399
400 if (bootverbose)
401 cbb_print_config(brdev);
402
403 /* Start the thread */
404 if (kthread_create(cbb_event_thread, sc, &sc->event_thread,
405 "%s", device_get_nameunit(brdev))) {
406 device_printf(brdev, "unable to create event thread.\n");
407 panic("cbb_create_event_thread");
408 }
409 return (0);
410 err:
411 if (sc->irq_res)
412 bus_release_resource(brdev, SYS_RES_IRQ, 0, sc->irq_res);
413 if (sc->base_res) {
414 bus_release_resource(brdev, SYS_RES_MEMORY, CBBR_SOCKBASE,
415 sc->base_res);
416 }
417 return (ENOMEM);
418 }
419
420 static void
cbb_chipinit(struct cbb_softc * sc)421 cbb_chipinit(struct cbb_softc *sc)
422 {
423 uint32_t mux, sysctrl, reg;
424
425 /* Set CardBus latency timer */
426 if (pci_read_config(sc->dev, PCIR_SECLAT_1, 1) < 0x20)
427 pci_write_config(sc->dev, PCIR_SECLAT_1, 0x20, 1);
428
429 /* Set PCI latency timer */
430 if (pci_read_config(sc->dev, PCIR_LATTIMER, 1) < 0x20)
431 pci_write_config(sc->dev, PCIR_LATTIMER, 0x20, 1);
432
433 /* Enable memory access */
434 PCI_MASK_CONFIG(sc->dev, PCIR_COMMAND,
435 | PCIM_CMD_MEMEN
436 | PCIM_CMD_PORTEN
437 | PCIM_CMD_BUSMASTEREN, 2);
438
439 /* disable Legacy IO */
440 switch (sc->chipset) {
441 case CB_RF5C46X:
442 PCI_MASK_CONFIG(sc->dev, CBBR_BRIDGECTRL,
443 & ~(CBBM_BRIDGECTRL_RL_3E0_EN |
444 CBBM_BRIDGECTRL_RL_3E2_EN), 2);
445 break;
446 default:
447 pci_write_config(sc->dev, CBBR_LEGACY, 0x0, 4);
448 break;
449 }
450
451 /* Use PCI interrupt for interrupt routing */
452 PCI_MASK2_CONFIG(sc->dev, CBBR_BRIDGECTRL,
453 & ~(CBBM_BRIDGECTRL_MASTER_ABORT |
454 CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN),
455 | CBBM_BRIDGECTRL_WRITE_POST_EN,
456 2);
457
458 /*
459 * XXX this should be a function table, ala OLDCARD. This means
460 * that we could more easily support ISA interrupts for pccard
461 * cards if we had to.
462 */
463 switch (sc->chipset) {
464 case CB_TI113X:
465 /*
466 * The TI 1031, TI 1130 and TI 1131 all require another bit
467 * be set to enable PCI routing of interrupts, and then
468 * a bit for each of the CSC and Function interrupts we
469 * want routed.
470 */
471 PCI_MASK_CONFIG(sc->dev, CBBR_CBCTRL,
472 | CBBM_CBCTRL_113X_PCI_INTR |
473 CBBM_CBCTRL_113X_PCI_CSC | CBBM_CBCTRL_113X_PCI_IRQ_EN,
474 1);
475 PCI_MASK_CONFIG(sc->dev, CBBR_DEVCTRL,
476 & ~(CBBM_DEVCTRL_INT_SERIAL |
477 CBBM_DEVCTRL_INT_PCI), 1);
478 break;
479 case CB_TI12XX:
480 /*
481 * Some TI 12xx (and [14][45]xx) based pci cards
482 * sometimes have issues with the MFUNC register not
483 * being initialized due to a bad EEPROM on board.
484 * Laptops that this matters on have this register
485 * properly initialized.
486 *
487 * The TI125X parts have a different register.
488 */
489 mux = pci_read_config(sc->dev, CBBR_MFUNC, 4);
490 sysctrl = pci_read_config(sc->dev, CBBR_SYSCTRL, 4);
491 if (mux == 0) {
492 mux = (mux & ~CBBM_MFUNC_PIN0) |
493 CBBM_MFUNC_PIN0_INTA;
494 if ((sysctrl & CBBM_SYSCTRL_INTRTIE) == 0)
495 mux = (mux & ~CBBM_MFUNC_PIN1) |
496 CBBM_MFUNC_PIN1_INTB;
497 pci_write_config(sc->dev, CBBR_MFUNC, mux, 4);
498 }
499 /*FALLTHROUGH*/
500 case CB_TI125X:
501 /*
502 * Disable zoom video. Some machines initialize this
503 * improperly and exerpience has shown that this helps
504 * prevent strange behavior.
505 */
506 pci_write_config(sc->dev, CBBR_MMCTRL, 0, 4);
507 break;
508 case CB_O2MICRO:
509 /*
510 * Issue #1: INT# generated at the same time as
511 * selected ISA IRQ. When IREQ# or STSCHG# is active,
512 * in addition to the ISA IRQ being generated, INT#
513 * will also be generated at the same time.
514 *
515 * Some of the older controllers have an issue in
516 * which the slot's PCI INT# will be asserted whenever
517 * IREQ# or STSCGH# is asserted even if ExCA registers
518 * 03h or 05h have an ISA IRQ selected.
519 *
520 * The fix for this issue, which will work for any
521 * controller (old or new), is to set ExCA registers
522 * 3Ah (slot 0) & 7Ah (slot 1) bits 7:4 = 1010b.
523 * These bits are undocumented. By setting this
524 * register (of each slot) to '1010xxxxb' a routing of
525 * IREQ# to INTC# and STSCHG# to INTC# is selected.
526 * Since INTC# isn't connected there will be no
527 * unexpected PCI INT when IREQ# or STSCHG# is active.
528 * However, INTA# (slot 0) or INTB# (slot 1) will
529 * still be correctly generated if NO ISA IRQ is
530 * selected (ExCA regs 03h or 05h are cleared).
531 */
532 reg = exca_getb(&sc->exca[0], EXCA_O2MICRO_CTRL_C);
533 reg = (reg & 0x0f) |
534 EXCA_O2CC_IREQ_INTC | EXCA_O2CC_STSCHG_INTC;
535 exca_putb(&sc->exca[0], EXCA_O2MICRO_CTRL_C, reg);
536
537 break;
538 case CB_TOPIC97:
539 /*
540 * Disable Zoom Video, ToPIC 97, 100.
541 */
542 pci_write_config(sc->dev, CBBR_TOPIC_ZV_CONTROL, 0, 1);
543 /*
544 * ToPIC 97, 100
545 * At offset 0xa1: INTERRUPT CONTROL register
546 * 0x1: Turn on INT interrupts.
547 */
548 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_INTCTRL,
549 | CBBM_TOPIC_INTCTRL_INTIRQSEL, 1);
550 goto topic_common;
551 case CB_TOPIC95:
552 /*
553 * SOCKETCTRL appears to be TOPIC 95/B specific
554 */
555 PCI_MASK_CONFIG(sc->dev, CBBR_TOPIC_SOCKETCTRL,
556 | CBBM_TOPIC_SOCKETCTRL_SCR_IRQSEL, 4);
557
558 topic_common:;
559 /*
560 * At offset 0xa0: SLOT CONTROL
561 * 0x80 Enable CardBus Functionality
562 * 0x40 Enable CardBus and PC Card registers
563 * 0x20 Lock ID in exca regs
564 * 0x10 Write protect ID in config regs
565 * Clear the rest of the bits, which defaults the slot
566 * in legacy mode to 0x3e0 and offset 0. (legacy
567 * mode is determined elsewhere)
568 */
569 pci_write_config(sc->dev, CBBR_TOPIC_SLOTCTRL,
570 CBBM_TOPIC_SLOTCTRL_SLOTON |
571 CBBM_TOPIC_SLOTCTRL_SLOTEN |
572 CBBM_TOPIC_SLOTCTRL_ID_LOCK |
573 CBBM_TOPIC_SLOTCTRL_ID_WP, 1);
574
575 /*
576 * At offset 0xa3 Card Detect Control Register
577 * 0x80 CARDBUS enbale
578 * 0x01 Cleared for hardware change detect
579 */
580 PCI_MASK2_CONFIG(sc->dev, CBBR_TOPIC_CDC,
581 | CBBM_TOPIC_CDC_CARDBUS,
582 & ~CBBM_TOPIC_CDC_SWDETECT, 4);
583 break;
584 }
585
586 /*
587 * Need to tell ExCA registers to CSC interrupts route via PCI
588 * interrupts. There are two ways to do this. Once is to set
589 * INTR_ENABLE and the other is to set CSC to 0. Since both
590 * methods are mutually compatible, we do both.
591 */
592 exca_putb(&sc->exca[0], EXCA_INTR, EXCA_INTR_ENABLE);
593 exca_putb(&sc->exca[0], EXCA_CSC_INTR, 0);
594
595 cbb_disable_func_intr(sc);
596
597 /* close all memory and io windows */
598 pci_write_config(sc->dev, CBBR_MEMBASE0, 0xffffffff, 4);
599 pci_write_config(sc->dev, CBBR_MEMLIMIT0, 0, 4);
600 pci_write_config(sc->dev, CBBR_MEMBASE1, 0xffffffff, 4);
601 pci_write_config(sc->dev, CBBR_MEMLIMIT1, 0, 4);
602 pci_write_config(sc->dev, CBBR_IOBASE0, 0xffffffff, 4);
603 pci_write_config(sc->dev, CBBR_IOLIMIT0, 0, 4);
604 pci_write_config(sc->dev, CBBR_IOBASE1, 0xffffffff, 4);
605 pci_write_config(sc->dev, CBBR_IOLIMIT1, 0, 4);
606 }
607
608 static int
cbb_route_interrupt(device_t pcib,device_t dev,int pin)609 cbb_route_interrupt(device_t pcib, device_t dev, int pin)
610 {
611 struct cbb_softc *sc = (struct cbb_softc *)device_get_softc(pcib);
612
613 return (rman_get_start(sc->irq_res));
614 }
615
616 static device_method_t cbb_methods[] = {
617 /* Device interface */
618 DEVMETHOD(device_probe, cbb_pci_probe),
619 DEVMETHOD(device_attach, cbb_pci_attach),
620 DEVMETHOD(device_detach, cbb_detach),
621 DEVMETHOD(device_shutdown, cbb_shutdown),
622 DEVMETHOD(device_suspend, cbb_suspend),
623 DEVMETHOD(device_resume, cbb_resume),
624
625 /* bus methods */
626 DEVMETHOD(bus_print_child, bus_generic_print_child),
627 DEVMETHOD(bus_read_ivar, cbb_read_ivar),
628 DEVMETHOD(bus_write_ivar, cbb_write_ivar),
629 DEVMETHOD(bus_alloc_resource, cbb_alloc_resource),
630 DEVMETHOD(bus_release_resource, cbb_release_resource),
631 DEVMETHOD(bus_activate_resource, cbb_activate_resource),
632 DEVMETHOD(bus_deactivate_resource, cbb_deactivate_resource),
633 DEVMETHOD(bus_driver_added, cbb_driver_added),
634 DEVMETHOD(bus_child_detached, cbb_child_detached),
635 DEVMETHOD(bus_setup_intr, cbb_setup_intr),
636 DEVMETHOD(bus_teardown_intr, cbb_teardown_intr),
637 DEVMETHOD(bus_child_present, cbb_child_present),
638
639 /* 16-bit card interface */
640 DEVMETHOD(card_set_res_flags, cbb_pcic_set_res_flags),
641 DEVMETHOD(card_set_memory_offset, cbb_pcic_set_memory_offset),
642
643 /* power interface */
644 DEVMETHOD(power_enable_socket, cbb_power_enable_socket),
645 DEVMETHOD(power_disable_socket, cbb_power_disable_socket),
646
647 /* pcib compatibility interface */
648 DEVMETHOD(pcib_maxslots, cbb_maxslots),
649 DEVMETHOD(pcib_read_config, cbb_read_config),
650 DEVMETHOD(pcib_write_config, cbb_write_config),
651 DEVMETHOD(pcib_route_interrupt, cbb_route_interrupt),
652
653 DEVMETHOD_END
654 };
655
656 static driver_t cbb_driver = {
657 "cbb",
658 cbb_methods,
659 sizeof(struct cbb_softc)
660 };
661
662 DRIVER_MODULE(cbb, pci, cbb_driver, cbb_devclass, NULL, NULL);
663 MODULE_DEPEND(cbb, exca, 1, 1, 1);
664