1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: src/sys/dev/bge/if_bgereg.h,v 1.1.2.16 2004/09/23 20:11:18 ps Exp $ 34 */ 35 36 #ifndef _IF_BNXVAR_H_ 37 #define _IF_BNXVAR_H_ 38 39 /* 40 * Tigon general information block. This resides in host memory 41 * and contains the status counters, ring control blocks and 42 * producer pointers. 43 */ 44 45 struct bnx_gib { 46 struct bge_stats bnx_stats; 47 struct bge_rcb bnx_tx_rcb[16]; 48 struct bge_rcb bnx_std_rx_rcb; 49 struct bge_rcb bnx_jumbo_rx_rcb; 50 struct bge_rcb bnx_mini_rx_rcb; 51 struct bge_rcb bnx_return_rcb; 52 }; 53 54 #define BNX_MIN_FRAMELEN 60 55 #define BNX_MAX_FRAMELEN 1536 56 #define BNX_JUMBO_FRAMELEN 9018 57 #define BNX_JUMBO_MTU (BNX_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 58 59 #define BNX_TIMEOUT 5000 60 #define BNX_FIRMWARE_TIMEOUT 100000 61 #define BNX_TXCONS_UNSET 0xFFFF /* impossible value */ 62 63 /* 64 * Other utility macros. 65 */ 66 #define BNX_INC(x, y) (x) = ((x) + 1) % (y) 67 68 /* 69 * BAR0 MAC register access macros. The Tigon always uses memory mapped 70 * register accesses and all registers must be accessed with 32 bit 71 * operations. 72 */ 73 74 #define CSR_WRITE_4(sc, reg, val) \ 75 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) 76 77 #define CSR_READ_4(sc, reg) \ 78 bus_space_read_4(sc->bnx_btag, sc->bnx_bhandle, reg) 79 80 #define BNX_SETBIT(sc, reg, x) \ 81 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x)) 82 83 #define BNX_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x)) 85 86 /* BAR2 APE register access macros. */ 87 #define APE_WRITE_4(sc, reg, val) \ 88 bus_write_4(sc->bnx_res2, reg, val) 89 90 #define APE_READ_4(sc, reg) \ 91 bus_read_4(sc->bnx_res2, reg) 92 93 #define APE_SETBIT(sc, reg, x) \ 94 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 95 #define APE_CLRBIT(sc, reg, x) \ 96 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 97 98 #define BNX_MEMWIN_READ(sc, x, val) \ 99 do { \ 100 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 101 (0xFFFF0000 & x), 4); \ 102 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 103 } while(0) 104 105 #define BNX_MEMWIN_WRITE(sc, x, val) \ 106 do { \ 107 pci_write_config(sc->bnx_dev, BGE_PCI_MEMWIN_BASEADDR, \ 108 (0xFFFF0000 & x), 4); \ 109 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 110 } while(0) 111 112 #define RCB_WRITE_4(sc, rcb, offset, val) \ 113 bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, \ 114 rcb + offsetof(struct bge_rcb, offset), val) 115 116 /* 117 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 118 * values are tuneable. They control the actual amount of buffers 119 * allocated for the standard, mini and jumbo receive rings. 120 */ 121 122 #define BNX_SSLOTS 256 123 #define BNX_MSLOTS 256 124 #define BNX_JSLOTS 384 125 126 #define BNX_JRAWLEN (BNX_JUMBO_FRAMELEN + ETHER_ALIGN) 127 #define BNX_JLEN (BNX_JRAWLEN + \ 128 (sizeof(uint64_t) - BNX_JRAWLEN % sizeof(uint64_t))) 129 #define BNX_JPAGESZ PAGE_SIZE 130 #define BNX_RESID (BNX_JPAGESZ - (BNX_JLEN * BNX_JSLOTS) % BNX_JPAGESZ) 131 #define BNX_JMEM ((BNX_JLEN * BNX_JSLOTS) + BNX_RESID) 132 133 struct bnx_softc; 134 struct bnx_tx_ring; 135 136 struct bnx_jslot { 137 struct bnx_softc *bnx_sc; 138 void *bnx_buf; 139 bus_addr_t bnx_paddr; 140 int bnx_inuse; 141 int bnx_slot; 142 SLIST_ENTRY(bnx_jslot) jslot_link; 143 }; 144 145 /* 146 * Ring structures. Most of these reside in host memory and we tell 147 * the NIC where they are via the ring control blocks. The exceptions 148 * are the tx and command rings, which live in NIC memory and which 149 * we access via the shared memory window. 150 */ 151 struct bnx_ring_data { 152 struct bge_rx_bd *bnx_rx_jumbo_ring; 153 bus_addr_t bnx_rx_jumbo_ring_paddr; 154 void *bnx_jumbo_buf; 155 struct bnx_gib bnx_info; 156 }; 157 158 struct bnx_rx_buf { 159 bus_dmamap_t bnx_rx_dmamap; 160 struct mbuf *bnx_rx_mbuf; 161 bus_addr_t bnx_rx_paddr; 162 int bnx_rx_len; 163 int bnx_rx_refilled; 164 } __cachealign; 165 166 struct bnx_rx_std_ring { 167 struct lwkt_serialize bnx_rx_std_serialize; 168 struct bnx_softc *bnx_sc; 169 170 uint16_t bnx_rx_std_stop; 171 uint16_t bnx_rx_std; /* current prod ring head */ 172 struct bge_rx_bd *bnx_rx_std_ring; 173 174 int bnx_rx_std_refill __cachealign; 175 int bnx_rx_std_used; 176 u_int bnx_rx_std_running; 177 struct thread *bnx_rx_std_ithread; 178 179 struct bnx_rx_buf bnx_rx_std_buf[BGE_STD_RX_RING_CNT]; 180 181 bus_dma_tag_t bnx_rx_mtag; /* RX mbuf DMA tag */ 182 183 bus_dma_tag_t bnx_rx_std_ring_tag; 184 bus_dmamap_t bnx_rx_std_ring_map; 185 bus_addr_t bnx_rx_std_ring_paddr; 186 } __cachealign; 187 188 struct bnx_rx_ret_ring { 189 struct lwkt_serialize bnx_rx_ret_serialize; 190 int bnx_rx_mbx; 191 uint32_t bnx_saved_status_tag; 192 volatile uint32_t *bnx_hw_status_tag; 193 int bnx_msix_mbx; 194 struct bnx_softc *bnx_sc; 195 struct bnx_rx_std_ring *bnx_std; 196 struct bnx_tx_ring *bnx_txr; 197 198 /* Shadow of bnx_rx_std_ring's bnx_rx_mtag */ 199 bus_dma_tag_t bnx_rx_mtag; 200 201 volatile uint16_t *bnx_rx_considx; 202 uint16_t bnx_rx_saved_considx; 203 uint16_t bnx_rx_cnt; 204 uint16_t bnx_rx_cntmax; 205 uint16_t bnx_rx_mask; 206 struct bge_rx_bd *bnx_rx_ret_ring; 207 bus_dmamap_t bnx_rx_tmpmap; 208 209 bus_dma_tag_t bnx_rx_ret_ring_tag; 210 bus_dmamap_t bnx_rx_ret_ring_map; 211 bus_addr_t bnx_rx_ret_ring_paddr; 212 213 u_long bnx_rx_pkt; 214 u_long bnx_rx_force_sched; 215 } __cachealign; 216 217 /* 218 * Mbuf pointers. We need these to keep track of the virtual addresses 219 * of our mbuf chains since we can only convert from physical to virtual, 220 * not the other way around. 221 */ 222 struct bnx_chain_data { 223 bus_dma_tag_t bnx_parent_tag; 224 bus_dma_tag_t bnx_rx_jumbo_ring_tag; 225 bus_dma_tag_t bnx_jumbo_tag; 226 bus_dmamap_t bnx_rx_jumbo_ring_map; 227 bus_dmamap_t bnx_jumbo_map; 228 struct bnx_rx_buf bnx_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 229 /* Stick the jumbo mem management stuff here too. */ 230 struct bnx_jslot bnx_jslots[BNX_JSLOTS]; 231 }; 232 233 struct bnx_tx_buf { 234 bus_dmamap_t bnx_tx_dmamap; 235 struct mbuf *bnx_tx_mbuf; 236 }; 237 238 struct bnx_tx_ring { 239 struct lwkt_serialize bnx_tx_serialize; 240 volatile uint32_t *bnx_hw_status_tag; 241 uint32_t bnx_saved_status_tag; 242 struct bnx_softc *bnx_sc; 243 struct ifaltq_subque *bnx_ifsq; 244 volatile uint16_t *bnx_tx_considx; 245 uint16_t bnx_tx_flags; 246 #define BNX_TX_FLAG_SHORTDMA 0x0001 247 #define BNX_TX_FLAG_FORCE_DEFRAG 0x0002 248 uint16_t bnx_tx_saved_considx; 249 int bnx_tx_cnt; 250 uint32_t bnx_tx_prodidx; 251 int bnx_tx_wreg; 252 int bnx_tx_mbx; 253 struct ifsubq_watchdog bnx_tx_watchdog; 254 255 struct bge_tx_bd *bnx_tx_ring; 256 257 bus_dma_tag_t bnx_tx_mtag; /* TX mbuf DMA tag */ 258 struct bnx_tx_buf bnx_tx_buf[BGE_TX_RING_CNT]; 259 260 bus_dma_tag_t bnx_tx_ring_tag; 261 bus_dmamap_t bnx_tx_ring_map; 262 bus_addr_t bnx_tx_ring_paddr; 263 int bnx_tx_cpuid; 264 265 u_long bnx_tx_pkt; 266 } __cachealign; 267 268 struct bnx_intr_data { 269 struct bnx_softc *bnx_sc; 270 struct bnx_rx_ret_ring *bnx_ret; 271 struct bnx_tx_ring *bnx_txr; 272 273 int bnx_intr_cpuid; 274 struct lwkt_serialize *bnx_intr_serialize; 275 struct callout bnx_intr_timer; 276 void (*bnx_intr_check)(void *); 277 uint16_t bnx_rx_check_considx; 278 uint16_t bnx_tx_check_considx; 279 boolean_t bnx_intr_maylose; 280 281 void *bnx_intr_arg; 282 driver_intr_t *bnx_intr_func; 283 void *bnx_intr_hand; 284 struct resource *bnx_intr_res; 285 int bnx_intr_rid; 286 int bnx_intr_mbx; 287 const uint32_t *bnx_saved_status_tag; 288 289 const char *bnx_intr_desc; 290 char bnx_intr_desc0[64]; 291 292 bus_dma_tag_t bnx_status_tag; 293 bus_dmamap_t bnx_status_map; 294 struct bge_status_block *bnx_status_block; 295 bus_addr_t bnx_status_block_paddr; 296 } __cachealign; 297 298 #define BNX_RX_RING_MAX 4 299 #define BNX_TX_RING_MAX 4 300 #define BNX_INTR_MAX 5 301 302 #define BNX_RDRTABLE_SIZE (BGE_RSS_INDIR_TBLENT_CNT * \ 303 BGE_RSS_INDIR_TBL_CNT) 304 305 struct bnx_softc { 306 struct arpcom arpcom; /* interface info */ 307 device_t bnx_dev; 308 device_t bnx_miibus; 309 bus_space_handle_t bnx_bhandle; 310 bus_space_tag_t bnx_btag; 311 struct resource *bnx_res; /* MAC mapped I/O */ 312 struct resource *bnx_res2; /* APE mapped I/O */ 313 struct ifmedia bnx_ifmedia; /* TBI media info */ 314 int bnx_pciecap; 315 uint32_t bnx_flags; /* BNX_FLAG_ */ 316 #define BNX_FLAG_TBI 0x00000001 317 #define BNX_FLAG_JUMBO 0x00000002 318 #define BNX_FLAG_APE 0x00000004 319 #define BNX_FLAG_5717_PLUS 0x00000008 320 #define BNX_FLAG_MII_SERDES 0x00000010 321 #define BNX_FLAG_CPMU 0x00000020 322 #define BNX_FLAG_57765_PLUS 0x00000040 323 #define BNX_FLAG_57765_FAMILY 0x00000080 324 #define BNX_FLAG_STATUSTAG_BUG 0x00000100 325 #define BNX_FLAG_TSO 0x00000200 326 #define BNX_FLAG_NO_EEPROM 0x10000000 327 #define BNX_FLAG_RXTX_BUNDLE 0x20000000 328 #define BNX_FLAG_STATUS_HASTAG 0x80000000 329 330 uint32_t bnx_mfw_flags; /* Management F/W flags */ 331 #define BNX_MFW_ON_RXCPU 0x00000001 332 #define BNX_MFW_ON_APE 0x00000002 333 #define BNX_MFW_TYPE_NCSI 0x00000004 334 #define BNX_MFW_TYPE_DASH 0x00000008 335 int bnx_phy_ape_lock; 336 int bnx_func_addr; 337 338 uint32_t bnx_chipid; 339 uint32_t bnx_asicrev; 340 uint32_t bnx_chiprev; 341 struct bnx_ring_data bnx_ldata; /* rings */ 342 struct bnx_chain_data bnx_cdata; /* mbufs */ 343 344 struct lwkt_serialize bnx_main_serialize; 345 volatile uint32_t *bnx_hw_status; 346 volatile uint32_t *bnx_hw_status_tag; 347 uint32_t bnx_saved_status_tag; 348 int bnx_link_evt; 349 u_long bnx_errors; 350 u_long bnx_norxbds; 351 352 int bnx_serialize_cnt; 353 struct lwkt_serialize **bnx_serialize; 354 355 int bnx_tx_ringcnt; 356 struct bnx_tx_ring *bnx_tx_ring; 357 int bnx_rx_retcnt; 358 struct bnx_rx_ret_ring *bnx_rx_ret_ring; 359 struct bnx_rx_std_ring bnx_rx_std_ring; 360 361 uint16_t bnx_jumbo; /* current jumo ring head */ 362 SLIST_HEAD(__bnx_jfreehead, bnx_jslot) bnx_jfree_listhead; 363 struct lwkt_serialize bnx_jslot_serializer; 364 uint32_t bnx_rx_coal_ticks; 365 uint32_t bnx_tx_coal_ticks; 366 uint32_t bnx_rx_coal_bds; 367 uint32_t bnx_rx_coal_bds_poll; 368 uint32_t bnx_tx_coal_bds; 369 uint32_t bnx_tx_coal_bds_poll; 370 uint32_t bnx_rx_coal_bds_int; 371 uint32_t bnx_tx_coal_bds_int; 372 uint32_t bnx_mi_mode; 373 int bnx_if_flags; 374 int bnx_link; 375 uint32_t bnx_rdma_wa; 376 int bnx_tick_cpuid; 377 struct callout bnx_tick_timer; 378 379 struct if_ringmap *bnx_tx_rmap; 380 struct if_ringmap *bnx_rx_rmap; 381 382 int bnx_msix_mem_rid; 383 struct resource *bnx_msix_mem_res; 384 int bnx_intr_type; 385 int bnx_intr_cnt; 386 struct bnx_intr_data bnx_intr_data[BNX_INTR_MAX]; 387 388 int bnx_rdr_table[BNX_RDRTABLE_SIZE]; 389 390 int bnx_phyno; 391 uint32_t bnx_coal_chg; 392 #define BNX_RX_COAL_TICKS_CHG 0x01 393 #define BNX_TX_COAL_TICKS_CHG 0x02 394 #define BNX_RX_COAL_BDS_CHG 0x04 395 #define BNX_TX_COAL_BDS_CHG 0x08 396 #define BNX_RX_COAL_BDS_INT_CHG 0x40 397 #define BNX_TX_COAL_BDS_INT_CHG 0x80 398 399 void (*bnx_link_upd)(struct bnx_softc *, uint32_t); 400 uint32_t bnx_link_chg; 401 402 int bnx_rss_debug; 403 #define BNX_TSO_NSTATS 45 404 u_long bnx_tsosegs[BNX_TSO_NSTATS]; 405 }; 406 407 #define BNX_NSEG_NEW 40 408 #define BNX_NSEG_SPARE 33 /* enough for 64K TSO segment */ 409 #define BNX_NSEG_RSVD 4 410 411 /* RX coalesce ticks, unit: us */ 412 #define BNX_RX_COAL_TICKS_MIN 0 413 #define BNX_RX_COAL_TICKS_DEF 160 414 #define BNX_RX_COAL_TICKS_MAX 1023 415 416 /* TX coalesce ticks, unit: us */ 417 #define BNX_TX_COAL_TICKS_MIN 0 418 #define BNX_TX_COAL_TICKS_DEF 1023 419 #define BNX_TX_COAL_TICKS_MAX 1023 420 421 /* RX coalesce BDs */ 422 #define BNX_RX_COAL_BDS_MIN 0 423 #define BNX_RX_COAL_BDS_DEF 0 424 #define BNX_RX_COAL_BDS_INT_DEF 80 425 #define BNX_RX_COAL_BDS_MAX 255 426 427 /* TX coalesce BDs */ 428 #define BNX_TX_COAL_BDS_MIN 0 429 #define BNX_TX_COAL_BDS_DEF 128 430 #define BNX_TX_COAL_BDS_POLL_DEF 64 431 #define BNX_TX_COAL_BDS_INT_DEF 64 432 #define BNX_TX_COAL_BDS_MAX 255 433 434 /* Number of segments sent before writing to TX related registers */ 435 #define BNX_TX_WREG_NSEGS 8 436 437 /* Return ring descriptor count */ 438 #define BNX_RETURN_RING_CNT 512 439 440 #define BNX_TX_RING_MAX 4 441 442 #define BNX_RSS_ENABLED(sc) ((sc)->bnx_rx_retcnt > 1) 443 444 #endif /* !_IF_BNXVAR_H_ */ 445