1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27
28 #include "include/logger_interface.h"
29
30 #include "irq_service_dce120.h"
31 #include "../dce110/irq_service_dce110.h"
32
33 #include "dce/dce_12_0_offset.h"
34 #include "dce/dce_12_0_sh_mask.h"
35 #include "soc15_hw_ip.h"
36 #include "vega10_ip_offset.h"
37
38 #include "ivsrcid/ivsrcid_vislands30.h"
39
hpd_ack(struct irq_service * irq_service,const struct irq_source_info * info)40 static bool hpd_ack(
41 struct irq_service *irq_service,
42 const struct irq_source_info *info)
43 {
44 uint32_t addr = info->status_reg;
45 uint32_t value = dm_read_reg(irq_service->ctx, addr);
46 uint32_t current_status =
47 get_reg_field_value(
48 value,
49 HPD0_DC_HPD_INT_STATUS,
50 DC_HPD_SENSE_DELAYED);
51
52 dal_irq_service_ack_generic(irq_service, info);
53
54 value = dm_read_reg(irq_service->ctx, info->enable_reg);
55
56 set_reg_field_value(
57 value,
58 current_status ? 0 : 1,
59 HPD0_DC_HPD_INT_CONTROL,
60 DC_HPD_INT_POLARITY);
61
62 dm_write_reg(irq_service->ctx, info->enable_reg, value);
63
64 return true;
65 }
66
67 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
68 .set = NULL,
69 .ack = hpd_ack
70 };
71
72 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
73 .set = NULL,
74 .ack = NULL
75 };
76
77 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
78 .set = NULL,
79 .ack = NULL
80 };
81
82 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
83 .set = dce110_vblank_set,
84 .ack = NULL
85 };
86
87 #define BASE_INNER(seg) \
88 DCE_BASE__INST0_SEG ## seg
89
90 #define BASE(seg) \
91 BASE_INNER(seg)
92
93 #define SRI(reg_name, block, id)\
94 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
95 mm ## block ## id ## _ ## reg_name
96
97
98 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
99 .enable_reg = SRI(reg1, block, reg_num),\
100 .enable_mask = \
101 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
102 .enable_value = {\
103 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
104 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
105 },\
106 .ack_reg = SRI(reg2, block, reg_num),\
107 .ack_mask = \
108 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
109 .ack_value = \
110 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
111
112 #define hpd_int_entry(reg_num)\
113 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
114 IRQ_REG_ENTRY(HPD, reg_num,\
115 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
116 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
117 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
118 .funcs = &hpd_irq_info_funcs\
119 }
120
121 #define hpd_rx_int_entry(reg_num)\
122 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
123 IRQ_REG_ENTRY(HPD, reg_num,\
124 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
125 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
126 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
127 .funcs = &hpd_rx_irq_info_funcs\
128 }
129 #define pflip_int_entry(reg_num)\
130 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
131 IRQ_REG_ENTRY(DCP, reg_num, \
132 GRPH_INTERRUPT_CONTROL, GRPH_PFLIP_INT_MASK, \
133 GRPH_INTERRUPT_STATUS, GRPH_PFLIP_INT_CLEAR),\
134 .status_reg = SRI(GRPH_INTERRUPT_STATUS, DCP, reg_num),\
135 .funcs = &pflip_irq_info_funcs\
136 }
137
138 #define vupdate_int_entry(reg_num)\
139 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
140 IRQ_REG_ENTRY(CRTC, reg_num,\
141 CRTC_INTERRUPT_CONTROL, CRTC_V_UPDATE_INT_MSK,\
142 CRTC_V_UPDATE_INT_STATUS, CRTC_V_UPDATE_INT_CLEAR),\
143 .funcs = &vblank_irq_info_funcs\
144 }
145
146 #define vblank_int_entry(reg_num)\
147 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
148 IRQ_REG_ENTRY(CRTC, reg_num,\
149 CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_INT_ENABLE,\
150 CRTC_VERTICAL_INTERRUPT0_CONTROL, CRTC_VERTICAL_INTERRUPT0_CLEAR),\
151 .funcs = &vblank_irq_info_funcs,\
152 .src_id = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0 + reg_num\
153 }
154
155 #define dummy_irq_entry() \
156 {\
157 .funcs = &dummy_irq_info_funcs\
158 }
159
160 #define i2c_int_entry(reg_num) \
161 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
162
163 #define dp_sink_int_entry(reg_num) \
164 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
165
166 #define gpio_pad_int_entry(reg_num) \
167 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
168
169 #define dc_underflow_int_entry(reg_num) \
170 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
171
172 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
173 .set = dal_irq_service_dummy_set,
174 .ack = dal_irq_service_dummy_ack
175 };
176
177 static const struct irq_source_info
178 irq_source_info_dce120[DAL_IRQ_SOURCES_NUMBER] = {
179 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
180 hpd_int_entry(0),
181 hpd_int_entry(1),
182 hpd_int_entry(2),
183 hpd_int_entry(3),
184 hpd_int_entry(4),
185 hpd_int_entry(5),
186 hpd_rx_int_entry(0),
187 hpd_rx_int_entry(1),
188 hpd_rx_int_entry(2),
189 hpd_rx_int_entry(3),
190 hpd_rx_int_entry(4),
191 hpd_rx_int_entry(5),
192 i2c_int_entry(1),
193 i2c_int_entry(2),
194 i2c_int_entry(3),
195 i2c_int_entry(4),
196 i2c_int_entry(5),
197 i2c_int_entry(6),
198 dp_sink_int_entry(1),
199 dp_sink_int_entry(2),
200 dp_sink_int_entry(3),
201 dp_sink_int_entry(4),
202 dp_sink_int_entry(5),
203 dp_sink_int_entry(6),
204 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
205 pflip_int_entry(0),
206 pflip_int_entry(1),
207 pflip_int_entry(2),
208 pflip_int_entry(3),
209 pflip_int_entry(4),
210 pflip_int_entry(5),
211 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
212 gpio_pad_int_entry(0),
213 gpio_pad_int_entry(1),
214 gpio_pad_int_entry(2),
215 gpio_pad_int_entry(3),
216 gpio_pad_int_entry(4),
217 gpio_pad_int_entry(5),
218 gpio_pad_int_entry(6),
219 gpio_pad_int_entry(7),
220 gpio_pad_int_entry(8),
221 gpio_pad_int_entry(9),
222 gpio_pad_int_entry(10),
223 gpio_pad_int_entry(11),
224 gpio_pad_int_entry(12),
225 gpio_pad_int_entry(13),
226 gpio_pad_int_entry(14),
227 gpio_pad_int_entry(15),
228 gpio_pad_int_entry(16),
229 gpio_pad_int_entry(17),
230 gpio_pad_int_entry(18),
231 gpio_pad_int_entry(19),
232 gpio_pad_int_entry(20),
233 gpio_pad_int_entry(21),
234 gpio_pad_int_entry(22),
235 gpio_pad_int_entry(23),
236 gpio_pad_int_entry(24),
237 gpio_pad_int_entry(25),
238 gpio_pad_int_entry(26),
239 gpio_pad_int_entry(27),
240 gpio_pad_int_entry(28),
241 gpio_pad_int_entry(29),
242 gpio_pad_int_entry(30),
243 dc_underflow_int_entry(1),
244 dc_underflow_int_entry(2),
245 dc_underflow_int_entry(3),
246 dc_underflow_int_entry(4),
247 dc_underflow_int_entry(5),
248 dc_underflow_int_entry(6),
249 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
250 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
251 vupdate_int_entry(0),
252 vupdate_int_entry(1),
253 vupdate_int_entry(2),
254 vupdate_int_entry(3),
255 vupdate_int_entry(4),
256 vupdate_int_entry(5),
257 vblank_int_entry(0),
258 vblank_int_entry(1),
259 vblank_int_entry(2),
260 vblank_int_entry(3),
261 vblank_int_entry(4),
262 vblank_int_entry(5),
263 };
264
265 static const struct irq_service_funcs irq_service_funcs_dce120 = {
266 .to_dal_irq_source = to_dal_irq_source_dce110
267 };
268
construct(struct irq_service * irq_service,struct irq_service_init_data * init_data)269 static void construct(
270 struct irq_service *irq_service,
271 struct irq_service_init_data *init_data)
272 {
273 dal_irq_service_construct(irq_service, init_data);
274
275 irq_service->info = irq_source_info_dce120;
276 irq_service->funcs = &irq_service_funcs_dce120;
277 }
278
dal_irq_service_dce120_create(struct irq_service_init_data * init_data)279 struct irq_service *dal_irq_service_dce120_create(
280 struct irq_service_init_data *init_data)
281 {
282 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
283 GFP_KERNEL);
284
285 if (!irq_service)
286 return NULL;
287
288 construct(irq_service, init_data);
289 return irq_service;
290 }
291