xref: /dragonfly/sys/dev/drm/amd/amdgpu/Makefile (revision 40e07378e60653c3fc2fe3974fcb86d3f4eaedf9) 
1#
2# Makefile for the drm/amdgpu driver.
3#
4
5KMOD=     amdgpu
6
7.PATH:    ${.CURDIR}/../../scheduler \
8          ${.CURDIR}/../powerplay \
9          ${.CURDIR}/../powerplay/hwmgr \
10          ${.CURDIR}/../powerplay/smumgr \
11          ${.CURDIR}/../lib \
12          ${.CURDIR}/../display/amdgpu_dm \
13          ${.CURDIR}/../display/dc \
14          ${.CURDIR}/../display/dc/basics \
15          ${.CURDIR}/../display/dc/bios \
16          ${.CURDIR}/../display/dc/bios/dce80 \
17          ${.CURDIR}/../display/dc/bios/dce110 \
18          ${.CURDIR}/../display/dc/bios/dce112 \
19          ${.CURDIR}/../display/dc/calcs \
20          ${.CURDIR}/../display/dc/core \
21          ${.CURDIR}/../display/dc/dce \
22          ${.CURDIR}/../display/dc/gpio \
23          ${.CURDIR}/../display/dc/gpio/dce110 \
24          ${.CURDIR}/../display/dc/gpio/dce120 \
25          ${.CURDIR}/../display/dc/gpio/dce80 \
26          ${.CURDIR}/../display/dc/gpio/dcn10 \
27          ${.CURDIR}/../display/dc/gpio/diagnostics \
28          ${.CURDIR}/../display/dc/i2caux \
29          ${.CURDIR}/../display/dc/i2caux/dce100 \
30          ${.CURDIR}/../display/dc/i2caux/dce110 \
31          ${.CURDIR}/../display/dc/i2caux/dce112 \
32          ${.CURDIR}/../display/dc/i2caux/dce120 \
33          ${.CURDIR}/../display/dc/i2caux/dce80 \
34          ${.CURDIR}/../display/dc/i2caux/dcn10 \
35          ${.CURDIR}/../display/dc/i2caux/diagnostics \
36          ${.CURDIR}/../display/dc/irq \
37          ${.CURDIR}/../display/dc/irq/dce110 \
38          ${.CURDIR}/../display/dc/irq/dce120 \
39          ${.CURDIR}/../display/dc/irq/dce80 \
40          ${.CURDIR}/../display/dc/irq/dcn10 \
41          ${.CURDIR}/../display/dc/virtual \
42          ${.CURDIR}/../display/dc/dcn10 \
43          ${.CURDIR}/../display/dc/dml \
44          ${.CURDIR}/../display/dc/dce120 \
45          ${.CURDIR}/../display/dc/dce112 \
46          ${.CURDIR}/../display/dc/dce110 \
47          ${.CURDIR}/../display/dc/dce100 \
48          ${.CURDIR}/../display/dc/dce80 \
49          ${.CURDIR}/../display/modules/freesync \
50          ${.CURDIR}/../display/modules/color
51
52SRCS=     amdgpu_drv.c
53
54SRCS+=    chash.c
55
56# add KMS driver
57SRCS+= amdgpu_device.c amdgpu_kms.c \
58          amdgpu_atombios.c atombios_crtc.c amdgpu_connectors.c \
59          atom.c amdgpu_fence.c amdgpu_ttm.c amdgpu_object.c amdgpu_gart.c \
60          amdgpu_encoders.c amdgpu_display.c amdgpu_i2c.c \
61          amdgpu_fb.c amdgpu_gem.c amdgpu_ring.c \
62          amdgpu_cs.c amdgpu_bios.c amdgpu_benchmark.c amdgpu_test.c \
63          amdgpu_pm.c atombios_dp.c amdgpu_afmt.c amdgpu_trace_points.c \
64          atombios_encoders.c amdgpu_sa.c atombios_i2c.c \
65          amdgpu_prime.c amdgpu_vm.c amdgpu_ib.c amdgpu_pll.c \
66          amdgpu_ucode.c amdgpu_bo_list.c amdgpu_ctx.c amdgpu_sync.c \
67          amdgpu_gtt_mgr.c amdgpu_vram_mgr.c amdgpu_virt.c amdgpu_atomfirmware.c \
68          amdgpu_queue_mgr.c amdgpu_vf_error.c amdgpu_sched.c amdgpu_debugfs.c \
69          amdgpu_ids.c
70
71SRCS+= \
72          vi.c mxgpu_vi.c nbio_v6_1.c soc15.c emu_soc.c mxgpu_ai.c nbio_v7_0.c vega10_reg_init.c \
73          vega20_reg_init.c
74
75# add DF block
76SRCS+= \
77          df_v1_7.c \
78          df_v3_6.c
79
80# add GMC block
81SRCS+= \
82          gmc_v7_0.c \
83          gmc_v8_0.c \
84          gfxhub_v1_0.c mmhub_v1_0.c gmc_v9_0.c
85
86# add IH block
87SRCS+= \
88          amdgpu_irq.c \
89          amdgpu_ih.c \
90          iceland_ih.c \
91          tonga_ih.c \
92          cz_ih.c \
93          vega10_ih.c
94
95# add PSP block
96SRCS+= \
97          amdgpu_psp.c \
98          psp_v3_1.c \
99          psp_v10_0.c
100
101# add SMC block
102SRCS+= \
103          amdgpu_dpm.c
104
105# add DCE block
106SRCS+= \
107          dce_v10_0.c \
108          dce_v11_0.c \
109          dce_virtual.c
110
111# add GFX block
112SRCS+= \
113          amdgpu_gfx.c \
114          gfx_v8_0.c \
115          gfx_v9_0.c
116
117# add async DMA block
118SRCS+= \
119          sdma_v2_4.c \
120          sdma_v3_0.c \
121          sdma_v4_0.c
122
123# add UVD block
124SRCS+= \
125          amdgpu_uvd.c \
126          uvd_v5_0.c \
127          uvd_v6_0.c \
128          uvd_v7_0.c
129
130# add VCE block
131SRCS+= \
132          amdgpu_vce.c \
133          vce_v3_0.c \
134          vce_v4_0.c
135
136# add VCN block
137SRCS+= \
138          amdgpu_vcn.c \
139          vcn_v1_0.c
140
141# add amdkfd interfaces
142SRCS+= amdgpu_amdkfd.c
143
144# add cgs
145SRCS+= amdgpu_cgs.c
146
147# GPU scheduler
148SRCS+= \
149          gpu_scheduler.c \
150          sched_fence.c \
151          amdgpu_job.c
152
153SRCS+= amdgpu_acpi.c
154
155SRCS+= amd_powerplay.c
156
157# powerplay/hwmgr
158SRCS+= hwmgr.c processpptables.c \
159                    hardwaremanager.c smu8_hwmgr.c \
160                    pppcielanes.c\
161                    process_pptables_v1_0.c ppatomctrl.c ppatomfwctrl.c \
162                    smu7_hwmgr.c smu7_powertune.c smu7_thermal.c \
163                    smu7_clockpowergating.c \
164                    vega10_processpptables.c vega10_hwmgr.c vega10_powertune.c \
165                    vega10_thermal.c smu10_hwmgr.c pp_psm.c\
166                    vega12_processpptables.c vega12_hwmgr.c \
167                    vega12_thermal.c \
168                    pp_overdriver.c smu_helper.c
169
170# powerplay/smumgr
171SRCS+= smumgr.c smu8_smumgr.c tonga_smumgr.c fiji_smumgr.c \
172            polaris10_smumgr.c iceland_smumgr.c \
173            smu7_smumgr.c vega10_smumgr.c smu10_smumgr.c ci_smumgr.c \
174            vega12_smumgr.c vegam_smumgr.c smu9_smumgr.c
175
176# display core component (CONFIG_DRM_AMD_DC)
177# amdgpu_dm
178SRC+= amdgpu_dm.c amdgpu_dm_irq.c amdgpu_dm_mst_types.c amdgpu_dm_color.c
179# ifneq ($(CONFIG_DRM_AMD_DC),)
180SRC+= amdgpu_dm_services.c amdgpu_dm_helpers.c amdgpu_dm_pp_smu.c
181
182# dc
183SRCS+= amdgpu_dm.c amdgpu_dm_irq.c amdgpu_dm_mst_types.c amdgpu_dm_color.c
184SRCS+= amdgpu_dm_services.c amdgpu_dm_helpers.c amdgpu_dm_pp_smu.c
185
186# dc/basics
187SRCS+= conversion.c fixpt31_32.c \
188          log_helpers.c vector.c
189
190# dc/bios
191SRCS+= bios_parser.c bios_parser_interface.c  bios_parser_helper.c \
192          command_table.c command_table_helper.c bios_parser_common.c
193SRCS+= command_table2.c command_table_helper2.c bios_parser2.c
194# DCE 8x
195# All DCE8.x are derived from DCE8.0, so 8.0 MUST be defined if ANY of
196# DCE8.x is compiled.
197SRCS+= command_table_helper_dce80.c
198
199# DCE 11x
200SRCS+= command_table_helper_dce110.c
201SRCS+= command_table_helper_dce112.c
202SRCS+= command_table_helper2_dce112.c
203
204# dc/calcs
205SRCS+= dce_calcs.c bw_fixed.c custom_float.c
206
207# ifdef CONFIG_DRM_AMD_DC_DCN1_0
208SRCS+= dcn_calcs.c dcn_calc_math.c dcn_calc_auto.c
209
210# dc/dce
211SRCS+= dce_audio.c dce_stream_encoder.c dce_link_encoder.c dce_hwseq.c \
212          dce_mem_input.c dce_clock_source.c dce_scl_filters.c dce_transform.c \
213          dce_clocks.c dce_opp.c dce_dmcu.c dce_abm.c dce_ipp.c dce_aux.c
214
215# dc/gpio
216SRCS+= gpio_base.c gpio_service.c hw_factory.c \
217       hw_gpio.c hw_hpd.c hw_ddc.c hw_translate.c
218
219# DCE 8x
220# all DCE8.x are derived from DCE8.0
221SRCS+= hw_translate_dce80.c hw_factory_dce80.c
222
223# DCE 11x
224SRCS+= hw_translate_dce110.c hw_factory_dce110.c
225
226# DCE 12x
227SRCS+= hw_translate_dce120.c hw_factory_dce120.c
228
229# DCN 1x
230# ifdef CONFIG_DRM_AMD_DC_DCN1_0
231SRCS+= hw_translate_dcn10.c hw_factory_dcn10.c
232
233# Diagnostics on FPGA
234SRCS+= hw_translate_diag.c hw_factory_diag.c
235
236# dc/i2caux
237SRCS+= aux_engine.c engine_base.c i2caux.c i2c_engine.c \
238          i2c_generic_hw_engine.c i2c_hw_engine.c i2c_sw_engine.c
239# DCE 8x family
240SRCS+= i2caux_dce80.c i2c_hw_engine_dce80.c \
241          i2c_sw_engine_dce80.c
242
243# DCE 100 family
244SRCS+= i2caux_dce100.c
245
246# DCE 110 family
247SRCS+= i2caux_dce110.c i2c_sw_engine_dce110.c i2c_hw_engine_dce110.c \
248          aux_engine_dce110.c
249
250# DCE 112 family
251SRCS+= i2caux_dce112.c
252
253# DCN 1.0 family
254# ifdef CONFIG_DRM_AMD_DC_DCN1_0
255SRCS+= i2caux_dcn10.c
256
257# DCE 120 family
258SRCS+= i2caux_dce120.c
259
260SRCS+= i2caux_diag.c
261
262# dc/irq
263SRCS+= irq_service.c
264
265# DCE 8x
266SRCS+= irq_service_dce80.c
267
268# DCE 11x
269SRCS+= irq_service_dce110.c
270
271# DCE 12x
272SRCS+= irq_service_dce120.c
273
274# DCN 1x
275# ifdef CONFIG_DRM_AMD_DC_DCN1_0
276SRCS+= irq_service_dcn10.c
277
278# dc/virtual
279SRCS+= virtual_link_encoder.c virtual_stream_encoder.c
280
281# dc/dcn10
282SRCS+= dcn10_resource.c dcn10_ipp.c dcn10_hw_sequencer.c \
283          dcn10_dpp.c dcn10_opp.c dcn10_optc.c \
284          dcn10_hubp.c dcn10_mpc.c \
285          dcn10_dpp_dscl.c dcn10_dpp_cm.c dcn10_cm_common.c \
286          dcn10_hubbub.c dcn10_stream_encoder.c dcn10_link_encoder.c
287
288# dc/dml
289SRCS+= display_mode_lib.c display_rq_dlg_helpers.c dml1_display_rq_dlg_calc.c \
290          dml_common_defs.c
291
292# dc/dce120
293SRCS+= dce120_resource.c dce120_timing_generator.c \
294          dce120_hw_sequencer.c
295
296# dc/dce112
297SRCS+= dce112_compressor.c dce112_hw_sequencer.c \
298          dce112_resource.c
299
300# dc/dce110
301SRCS+= dce110_timing_generator.c \
302          dce110_compressor.c dce110_hw_sequencer.c dce110_resource.c \
303          dce110_opp_regamma_v.c dce110_opp_csc_v.c dce110_timing_generator_v.c \
304          dce110_mem_input_v.c dce110_opp_v.c dce110_transform_v.c
305
306# dc/dce100
307SRCS+= dce100_resource.c dce100_hw_sequencer.c
308
309# dc/dce80
310SRCS+= dce80_timing_generator.c dce80_hw_sequencer.c \
311          dce80_resource.c
312
313SRCS+= dc.c dc_link.c dc_resource.c dc_hw_sequencer.c dc_sink.c \
314          dc_surface.c dc_link_hwss.c dc_link_dp.c dc_link_ddc.c dc_debug.c dc_stream.c
315SRCS+= dc_helper.c
316
317# modules/freesync
318SRCS+= freesync.c
319
320# modules/color
321SRCS+= color_gamma.c
322# end display core component (CONFIG_DRM_AMD_DC)
323
324SRCS+= \
325          opt_ddb.h           \
326          opt_acpi.h          \
327          opt_drm.h           \
328          acpi_if.h \
329          bus_if.h  \
330          device_if.h         \
331          pci_if.h
332
333# From linux
334#TODO: remove when Timing Sync feature is complete
335KCFLAGS+= -DBUILD_FEATURE_TIMING_SYNC=0
336
337KCFLAGS+= -I${SYSDIR}/dev/drm/include
338KCFLAGS+= -I${SYSDIR}/dev/drm/include/drm
339KCFLAGS+= -I${SYSDIR}/dev/drm/include/uapi
340KCFLAGS+= -I${SYSDIR}/dev/drm/include/uapi/drm
341KCFLAGS+= -I${SYSDIR}/contrib/dev/acpica/source/include
342KCFLAGS+= -I${SYSDIR}/dev/drm/amd/amdgpu
343KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display
344KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/include
345KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/dc
346KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/dc/inc
347KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/dc/inc/hw
348KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/modules/inc
349KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/modules/freesync
350KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/modules/color
351KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/amdgpu_dm
352KCFLAGS+= -I${SYSDIR}/dev/drm/amd/display/include
353KCFLAGS+= -I${SYSDIR}/dev/drm/amd/include
354KCFLAGS+= -I${SYSDIR}/dev/drm/amd/include/asic_reg
355KCFLAGS+= -I${SYSDIR}/dev/drm/amd/powerplay/inc
356KCFLAGS+= -I${SYSDIR}/dev/drm/amd/powerplay/hwmgr
357KCFLAGS+= -I${SYSDIR}/dev/drm/amd/powerplay/smumgr
358KCFLAGS+= -I${SYSDIR}/dev/drm/scheduler
359KCFLAGS+= -include ${SYSDIR}/dev/drm/kconfig.h
360
361.include <bsd.kmod.mk>
362
363dcn_calcs.o:
364          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
365
366dcn_calc_auto.o:
367          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
368
369dcn_calc_math.o:
370          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
371
372dcn20_resource.o:
373          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
374
375dcn21_resource.o:
376          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
377
378dml1_display_rq_dlg_calc.o:
379          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
380
381dml_common_defs.o:
382          ${CC} ${CFLAGS} ${KCFLAGS} -mhard-float -msse -mpreferred-stack-boundary=4 -c ${.IMPSRC}
383