1 210 second timeout in CAM 3 4 5----- 6 7DELAY's might tsleep, so interrupts might run. fix poll loop to detect 8completion via other interrupts. 9 10Locking serialize_enter/exit. Lots of recursion. Needs help. Use 11lockmgr()? Needs to be converted to per-port locking, also. 12 13Port multiplier support (basics are now in) 14 15Simulate various mode pages (serial number access and so forth). 16 17NOTE RACE: When stopping a port explicitly which has not self stopped, 18i.e. CR is still on, we can race command completion and not have a good 19idea what bits to reload into CI etc to restart the commands that 20were running. This should only be done if we intend to reset the port. 21 22NOTE RACE: A transient IFS interrupt (fatal phy/protocol error) can occur 23when soft-resetting through a port multiplier, between the first and second 24FISes. We need to be able to lock access to the port. 25 26------ serial number ----------- 27 28OpenBSD /etc/devtab 29 30name type serialnumber 31 naa 32 wwn 33 serno 34 etc 35 36------ Misc probe info -------- 37 38<AHCI-PCI-SATA> port 39<S64A,NCQ,SSNTF,SALP,SAL,SCLO,PMD,SSC,PSC,CCCS,EMS>, 406 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps) 41 42ahci0: AHCI 1.2 capabilities 0xe3229f05 43<S64A,NCQ,SSNTF,SAL,SCLO,SPM,PMD>, 6 ports, 32 tags/port, gen 1 (1.5Gbps) and 2 (3Gbps) 44 450xf722ff83<S64A,NCQ,SSNTF,SMPS,SALP,SAL,SCLO,SPM,PMD,SSC,PSC,CCCS> 4 ports, 32 46 47 48Chipsets supporting FBSS (FIS-Based Switching): 49 SB800 50 S5000 (w/ ESB2) 51 (add more) 52--------------------------- 53 54Set device bits FIS: 55 56 EEEEEEEE HHHHLLLL NIRxxxxx FFFFFFFF 57 rrrrrrrr rrrrrrrr rrrrrrrr rrrrrrrr (reserved) 58 59 F8 FIS TYPE (0xA1) 60 N Notification bit 61 I Interrupt bit 62 R Reset bit 63 H4 Status hi (bit 3 is 'r' bit?) 64 L4 Status Lo (bit 3 is 'r' bit?) 65 E8 Error code 66 67 ATAPI/DISK notification: Word78 of IDENTIFY, 68 Use SET FEATURES to set. 69 70IDENTIFY DEVICE Changed in SATA 2: 71 72 Word 75 4:0 Max Queue depth 73 74 Word 76 9 Supports IPM requests 75 8 supports NCQ 76 7-4 reservedr 77 3 reserved 78 2 supports GEN2 79 1 supports GEN1 80 0 reserved (set to 0) 81 82 Word 78 4 supports in-order data delivery 83 3 supports IPMfrom device 84 2 supports DMA setup AA opt 85 1 supports non-zero buffer offssets in DMA setup 86 0 reserved (set to 0 87 88 Word 79 (sata features enabled) 89 90 91 Device configuration overlay 92 Word 0-7 Defined by ATA 93 Word 8 3 supports async notification 94 2 supports IPM 95 1 supports nz buffer offsets in DMA setup FIS 96 0 supports NCQ 97 Word 9 reserved for SATA 98 10-255 as defined by ATA 99 100SET FEATURES DEF 101 102 Feature 10h Enable use of SATA feature 103 feature 90h Disable use of SATA feature 104 105 sector count register contains specific feature to enable 106 107 01 No zero buffer offset in DMA setup fis 108 02 DMA setup fis AA opt 109 03 device initated power state transitions 110 04 guaranteed in-order data delivery 111 05 Asynchronous notification 112 113 114SCR REGISTERS 115 116 0 SStatus 117 1 SError 118 2 SControl 119 3 SActive 120 4 SNotification <---- 121 5-15 reserved 122