1 /* 2 * Exported interface to downloadable microcode for AdvanSys SCSI Adapters 3 * 4 * $FreeBSD: src/sys/dev/advansys/adwmcode.h,v 1.3 2000/02/03 16:34:57 gibbs Exp $ 5 * $DragonFly: src/sys/dev/disk/advansys/adwmcode.h,v 1.2 2003/06/17 04:28:21 dillon Exp $ 6 * 7 * Obtained from: 8 * 9 * Copyright (c) 1995-1999 Advanced System Products, Inc. 10 * All Rights Reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that redistributions of source 14 * code retain the above copyright notice and this comment without 15 * modification. 16 */ 17 18 #ifndef _ADMCODE_H_ 19 #define _ADMCODE_H_ 20 21 struct adw_mcode 22 { 23 const u_int8_t* mcode_buf; 24 const u_int32_t mcode_chksum; 25 const u_int16_t mcode_size; 26 }; 27 28 extern const struct adw_mcode adw_asc3550_mcode_data; 29 extern const struct adw_mcode adw_asc38C0800_mcode_data; 30 31 /* 32 * Fixed LRAM locations of microcode operating variables. 33 */ 34 #define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 35 #define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */ 36 #define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 37 #define ADW_MC_VERSION_DATE 0x0038 /* microcode version */ 38 #define ADW_MC_VERSION_NUM 0x003A /* microcode number */ 39 #define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 40 #define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 41 #define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 42 #define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */ 43 #define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 44 #define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 45 #define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 46 #define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 47 #define ADW_MC_CHIP_TYPE 0x009A 48 #define ADW_MC_INTRB_CODE 0x009B 49 #define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 50 #define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */ 51 #define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/ 52 #define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /* 53 * Host Initiated 54 * SCSI Bus Reset. 55 */ 56 #define ADW_MC_WDTR_ABLE_BIOS_31 0x0120 57 #define ADW_MC_WDTR_ABLE 0x009C 58 #define ADW_MC_SDTR_ABLE 0x009E 59 #define ADW_MC_TAGQNG_ABLE 0x00A0 60 #define ADW_MC_DISC_ENABLE 0x00A2 61 #define ADW_MC_IDLE_CMD_STATUS 0x00A4 62 #define ADW_MC_IDLE_CMD 0x00A6 63 #define ADW_MC_IDLE_CMD_PARAMETER 0x00A8 64 #define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC 65 #define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE 66 #define ADW_MC_DEFAULT_MEM_CFG 0x00B0 67 #define ADW_MC_DEFAULT_SEL_MASK 0x00B2 68 #define ADW_MC_RISC_NEXT_READY 0x00B4 69 #define ADW_MC_RISC_NEXT_DONE 0x00B5 70 #define ADW_MC_SDTR_DONE 0x00B6 71 #define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0 72 #define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0 73 #define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100 74 #define ADW_HSHK_CFG_WIDE_XFR 0x8000 75 #define ADW_HSHK_CFG_RATE_MASK 0x7F00 76 #define ADW_HSHK_CFG_RATE_SHIFT 8 77 #define ADW_HSHK_CFG_OFFSET 0x001F 78 #define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 79 #define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */ 80 #define ADW_MC_WDTR_DONE 0x0124 81 #define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 82 #define ADW_MC_ICQ 0x0160 83 #define ADW_MC_IRQ 0x0164 84 85 /* ADW_SCSI_REQ_Q 'cntl' field values */ 86 #define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */ 87 #define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 88 #define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 89 #define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 90 #define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */ 91 92 #define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 93 #define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 94 #define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/ 95 #define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 96 #define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/ 97 /* 98 * Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or 99 * ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 100 */ 101 #define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 102 #define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 103 104 struct adw_carrier 105 { 106 u_int32_t carr_offset; /* Carrier byte offset into our array */ 107 u_int32_t carr_ba; /* Carrier Bus Address */ 108 u_int32_t areq_ba; /* SCSI Req Queue Bus Address */ 109 u_int32_t next_ba; 110 #define ADW_RQ_DONE 0x00000001 111 #define ADW_CQ_STOPPER 0x00000000 112 #define ADW_NEXT_BA_MASK 0xFFFFFFF0 113 }; 114 115 /* 116 * Microcode idle loop commands 117 */ 118 typedef enum { 119 ADW_IDLE_CMD_COMPLETED = 0x0000, 120 ADW_IDLE_CMD_STOP_CHIP = 0x0001, 121 ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002, 122 ADW_IDLE_CMD_SEND_INT = 0x0004, 123 ADW_IDLE_CMD_ABORT = 0x0008, 124 ADW_IDLE_CMD_DEVICE_RESET = 0x0010, 125 ADW_IDLE_CMD_SCSI_RESET_START = 0x0020, 126 ADW_IDLE_CMD_SCSI_RESET_END = 0x0040, 127 ADW_IDLE_CMD_SCSIREQ = 0x0080 128 } adw_idle_cmd_t; 129 130 typedef enum { 131 ADW_IDLE_CMD_FAILURE = 0x0000, 132 ADW_IDLE_CMD_SUCCESS = 0x0001 133 } adw_idle_cmd_status_t; 134 135 136 #endif /* _ADMCODE_H_ */ 137