1 /*-
2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
10 * disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * $FreeBSD: src/sys/i386/pci/pci_bus.c,v 1.128.8.1 2009/04/15 03:14:26 kensmith Exp $
27 */
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/bus.h>
32 #include <sys/kernel.h>
33 #include <sys/malloc.h>
34 #include <sys/module.h>
35 #include <sys/sysctl.h>
36
37 #include <bus/pci/pcivar.h>
38 #include <bus/pci/pcireg.h>
39 #include <bus/pci/pcib_private.h>
40 #include <bus/isa/isavar.h>
41 #include <machine/md_var.h>
42
43 #include "legacyvar.h"
44 #include "pci_cfgreg.h"
45
46 #include "pcib_if.h"
47
48 #ifdef notyet
49 static int pcibios_pcib_route_interrupt(device_t pcib, device_t dev,
50 int pin);
51 #endif
52
53 int
legacy_pcib_maxslots(device_t dev)54 legacy_pcib_maxslots(device_t dev)
55 {
56 return 31;
57 }
58
59 /* read configuration space register */
60
61 u_int32_t
legacy_pcib_read_config(device_t dev,int bus,int slot,int func,int reg,int bytes)62 legacy_pcib_read_config(device_t dev, int bus, int slot, int func,
63 int reg, int bytes)
64 {
65 return(pci_cfgregread(bus, slot, func, reg, bytes));
66 }
67
68 /* write configuration space register */
69
70 void
legacy_pcib_write_config(device_t dev,int bus,int slot,int func,int reg,u_int32_t data,int bytes)71 legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
72 int reg, u_int32_t data, int bytes)
73 {
74 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
75 }
76
77 /* Pass MSI requests up to the nexus. */
78
79 static int
legacy_pcib_alloc_msi(device_t pcib,device_t dev,int count,int maxcount,int * irqs,int cpuid)80 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
81 int *irqs, int cpuid)
82 {
83 device_t bus;
84
85 bus = device_get_parent(pcib);
86 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
87 irqs, cpuid));
88 }
89
90 static int
legacy_pcib_alloc_msix(device_t pcib,device_t dev,int * irq,int cpuid)91 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq, int cpuid)
92 {
93 device_t bus;
94
95 bus = device_get_parent(pcib);
96 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq, cpuid));
97 }
98
99 static int
legacy_pcib_map_msi(device_t pcib,device_t dev,int irq,uint64_t * addr,uint32_t * data,int cpuid)100 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
101 uint32_t *data, int cpuid)
102 {
103 device_t bus;
104
105 bus = device_get_parent(pcib);
106 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data,
107 cpuid));
108 }
109
110 static const char *
legacy_pcib_is_host_bridge(int bus,int slot,int func,uint32_t id,uint8_t class,uint8_t subclass,uint8_t * busnum)111 legacy_pcib_is_host_bridge(int bus, int slot, int func,
112 uint32_t id, uint8_t class, uint8_t subclass,
113 uint8_t *busnum)
114 {
115 const char *s = NULL;
116 static uint8_t pxb[4]; /* hack for 450nx */
117
118 *busnum = 0;
119
120 switch (id) {
121 case 0x12258086:
122 s = "Intel 824?? host to PCI bridge";
123 /* XXX This is a guess */
124 /* *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x41, 1); */
125 *busnum = bus;
126 break;
127 case 0x71208086:
128 s = "Intel 82810 (i810 GMCH) Host To Hub bridge";
129 break;
130 case 0x71228086:
131 s = "Intel 82810-DC100 (i810-DC100 GMCH) Host To Hub bridge";
132 break;
133 case 0x71248086:
134 s = "Intel 82810E (i810E GMCH) Host To Hub bridge";
135 break;
136 case 0x11308086:
137 s = "Intel 82815 (i815 GMCH) Host To Hub bridge";
138 break;
139 case 0x71808086:
140 s = "Intel 82443LX (440 LX) host to PCI bridge";
141 break;
142 case 0x71908086:
143 s = "Intel 82443BX (440 BX) host to PCI bridge";
144 break;
145 case 0x71928086:
146 s = "Intel 82443BX host to PCI bridge (AGP disabled)";
147 break;
148 case 0x71948086:
149 s = "Intel 82443MX host to PCI bridge";
150 break;
151 case 0x71a08086:
152 s = "Intel 82443GX host to PCI bridge";
153 break;
154 case 0x71a18086:
155 s = "Intel 82443GX host to AGP bridge";
156 break;
157 case 0x71a28086:
158 s = "Intel 82443GX host to PCI bridge (AGP disabled)";
159 break;
160 case 0x84c48086:
161 s = "Intel 82454KX/GX (Orion) host to PCI bridge";
162 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x4a, 1);
163 break;
164 case 0x84ca8086:
165 /*
166 * For the 450nx chipset, there is a whole bundle of
167 * things pretending to be host bridges. The MIOC will
168 * be seen first and isn't really a pci bridge (the
169 * actual busses are attached to the PXB's). We need to
170 * read the registers of the MIOC to figure out the
171 * bus numbers for the PXB channels.
172 *
173 * Since the MIOC doesn't have a pci bus attached, we
174 * pretend it wasn't there.
175 */
176 pxb[0] = legacy_pcib_read_config(0, bus, slot, func,
177 0xd0, 1); /* BUSNO[0] */
178 pxb[1] = legacy_pcib_read_config(0, bus, slot, func,
179 0xd1, 1) + 1; /* SUBA[0]+1 */
180 pxb[2] = legacy_pcib_read_config(0, bus, slot, func,
181 0xd3, 1); /* BUSNO[1] */
182 pxb[3] = legacy_pcib_read_config(0, bus, slot, func,
183 0xd4, 1) + 1; /* SUBA[1]+1 */
184 return NULL;
185 case 0x84cb8086:
186 switch (slot) {
187 case 0x12:
188 s = "Intel 82454NX PXB#0, Bus#A";
189 *busnum = pxb[0];
190 break;
191 case 0x13:
192 s = "Intel 82454NX PXB#0, Bus#B";
193 *busnum = pxb[1];
194 break;
195 case 0x14:
196 s = "Intel 82454NX PXB#1, Bus#A";
197 *busnum = pxb[2];
198 break;
199 case 0x15:
200 s = "Intel 82454NX PXB#1, Bus#B";
201 *busnum = pxb[3];
202 break;
203 }
204 break;
205
206 /* AMD -- vendor 0x1022 */
207 case 0x70061022:
208 s = "AMD-751 host to PCI bridge";
209 break;
210 case 0x700e1022:
211 s = "AMD-761 host to PCI bridge";
212 break;
213
214 /* SiS -- vendor 0x1039 */
215 case 0x04961039:
216 s = "SiS 85c496";
217 break;
218 case 0x04061039:
219 s = "SiS 85c501";
220 break;
221 case 0x06011039:
222 s = "SiS 85c601";
223 break;
224 case 0x55911039:
225 s = "SiS 5591 host to PCI bridge";
226 break;
227 case 0x00011039:
228 s = "SiS 5591 host to AGP bridge";
229 break;
230
231 /* VLSI -- vendor 0x1004 */
232 case 0x00051004:
233 s = "VLSI 82C592 Host to PCI bridge";
234 break;
235
236 /* XXX Here is MVP3, I got the datasheet but NO M/B to test it */
237 /* totally. Please let me know if anything wrong. -F */
238 /* XXX need info on the MVP3 -- any takers? */
239 case 0x05981106:
240 s = "VIA 82C598MVP (Apollo MVP3) host bridge";
241 break;
242
243 /* AcerLabs -- vendor 0x10b9 */
244 /* Funny : The datasheet told me vendor id is "10b8",sub-vendor */
245 /* id is '10b9" but the register always shows "10b9". -Foxfair */
246 case 0x154110b9:
247 s = "AcerLabs M1541 (Aladdin-V) PCI host bridge";
248 break;
249
250 /* OPTi -- vendor 0x1045 */
251 case 0xc7011045:
252 s = "OPTi 82C700 host to PCI bridge";
253 break;
254 case 0xc8221045:
255 s = "OPTi 82C822 host to PCI Bridge";
256 break;
257
258 /* ServerWorks -- vendor 0x1166 */
259 case 0x00051166:
260 s = "ServerWorks NB6536 2.0HE host to PCI bridge";
261 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
262 break;
263
264 case 0x00061166:
265 /* FALLTHROUGH */
266 case 0x00081166:
267 /* FALLTHROUGH */
268 case 0x02011166:
269 /* FALLTHROUGH */
270 case 0x010f1014: /* IBM re-badged ServerWorks chipset */
271 s = "ServerWorks host to PCI bridge";
272 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
273 break;
274
275 case 0x00091166:
276 s = "ServerWorks NB6635 3.0LE host to PCI bridge";
277 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
278 break;
279
280 case 0x00101166:
281 s = "ServerWorks CIOB30 host to PCI bridge";
282 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
283 break;
284
285 case 0x00111166:
286 /* FALLTHROUGH */
287 case 0x03021014: /* IBM re-badged ServerWorks chipset */
288 s = "ServerWorks CMIC-HE host to PCI-X bridge";
289 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
290 break;
291
292 /* XXX unknown chipset, but working */
293 case 0x00171166:
294 /* FALLTHROUGH */
295 case 0x01011166:
296 s = "ServerWorks host to PCI bridge(unknown chipset)";
297 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0x44, 1);
298 break;
299
300 /* Compaq/HP -- vendor 0x0e11 */
301 case 0x60100e11:
302 s = "Compaq/HP Model 6010 HotPlug PCI Bridge";
303 *busnum = legacy_pcib_read_config(0, bus, slot, func, 0xc8, 1);
304 break;
305
306 /* Integrated Micro Solutions -- vendor 0x10e0 */
307 case 0x884910e0:
308 s = "Integrated Micro Solutions VL Bridge";
309 break;
310
311 default:
312 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
313 s = "Host to PCI bridge";
314 break;
315 }
316
317 return s;
318 }
319
320 /*
321 * Scan the first pci bus for host-pci bridges and add pcib instances
322 * to the nexus for each bridge.
323 */
324 static int
legacy_pcib_identify(driver_t * driver,device_t parent)325 legacy_pcib_identify(driver_t *driver, device_t parent)
326 {
327 int bus, slot, func;
328 u_int8_t hdrtype;
329 int found = 0;
330 int pcifunchigh;
331 int found824xx = 0;
332 int found_orion = 0;
333 device_t child;
334 devclass_t pci_devclass;
335
336 if (pci_cfgregopen() == 0)
337 return ENXIO;
338 /*
339 * Check to see if we haven't already had a PCI bus added
340 * via some other means. If we have, bail since otherwise
341 * we're going to end up duplicating it.
342 */
343 if ((pci_devclass = devclass_find("pci")) &&
344 devclass_get_device(pci_devclass, 0))
345 return ENXIO;
346
347 bus = 0;
348 retry:
349 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
350 func = 0;
351 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
352 PCIR_HDRTYPE, 1);
353 /*
354 * When enumerating bus devices, the standard says that
355 * one should check the header type and ignore the slots whose
356 * header types that the software doesn't know about. We use
357 * this to filter out devices.
358 */
359 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
360 continue;
361 if ((hdrtype & PCIM_MFDEV) &&
362 (!found_orion || hdrtype != 0xff))
363 pcifunchigh = PCI_FUNCMAX;
364 else
365 pcifunchigh = 0;
366 for (func = 0; func <= pcifunchigh; func++) {
367 /*
368 * Read the IDs and class from the device.
369 */
370 u_int32_t id;
371 u_int8_t class, subclass, busnum;
372 const char *s;
373 device_t *devs;
374 int ndevs, i;
375
376 id = legacy_pcib_read_config(0, bus, slot, func,
377 PCIR_DEVVENDOR, 4);
378 if (id == -1)
379 continue;
380 class = legacy_pcib_read_config(0, bus, slot, func,
381 PCIR_CLASS, 1);
382 subclass = legacy_pcib_read_config(0, bus, slot, func,
383 PCIR_SUBCLASS, 1);
384
385 s = legacy_pcib_is_host_bridge(bus, slot, func,
386 id, class, subclass,
387 &busnum);
388 if (s == NULL)
389 continue;
390
391 /*
392 * Check to see if the physical bus has already
393 * been seen. Eg: hybrid 32 and 64 bit host
394 * bridges to the same logical bus.
395 */
396 if (device_get_children(parent, &devs, &ndevs) == 0) {
397 for (i = 0; s != NULL && i < ndevs; i++) {
398 if (strcmp(device_get_name(devs[i]),
399 "pcib") != 0)
400 continue;
401 if (legacy_get_pcibus(devs[i]) == busnum)
402 s = NULL;
403 }
404 kfree(devs, M_TEMP);
405 }
406
407 if (s == NULL)
408 continue;
409
410 /*
411 * Add at priority 100 to make sure we
412 * go after any motherboard resources
413 */
414 child = BUS_ADD_CHILD(parent, parent, 100 + busnum,
415 "pcib", busnum);
416 device_set_desc(child, s);
417 legacy_set_pcibus(child, busnum);
418
419 found = 1;
420 if (id == 0x12258086)
421 found824xx = 1;
422 if (id == 0x84c48086)
423 found_orion = 1;
424 }
425 }
426 if (found824xx && bus == 0) {
427 bus++;
428 goto retry;
429 }
430
431 /*
432 * Make sure we add at least one bridge since some old
433 * hardware doesn't actually have a host-pci bridge device.
434 * Note that pci_cfgregopen() thinks we have PCI devices..
435 */
436 if (!found) {
437 if (bootverbose)
438 kprintf(
439 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
440 child = BUS_ADD_CHILD(parent, parent, 100, "pcib", 0);
441 legacy_set_pcibus(child, 0);
442 }
443 return 0;
444 }
445
446 static int
legacy_pcib_probe(device_t dev)447 legacy_pcib_probe(device_t dev)
448 {
449 if (pci_cfgregopen() == 0)
450 return ENXIO;
451 return -100;
452 }
453
454 static int
legacy_pcib_attach(device_t dev)455 legacy_pcib_attach(device_t dev)
456 {
457 #ifdef notyet
458 device_t pir;
459 #endif
460 int bus;
461
462 /*
463 * Look for a PCI BIOS interrupt routing table as that will be
464 * our method of routing interrupts if we have one.
465 */
466 bus = pcib_get_bus(dev);
467 #ifdef notyet
468 if (pci_pir_probe(bus, 0)) {
469 pir = BUS_ADD_CHILD(device_get_parent(dev), device_get_parent(dev), 0, "pir", 0);
470 if (pir != NULL)
471 device_probe_and_attach(pir);
472 }
473 #endif
474 device_add_child(dev, "pci", bus);
475 return bus_generic_attach(dev);
476 }
477
478 int
legacy_pcib_read_ivar(device_t dev,device_t child,int which,uintptr_t * result)479 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
480 uintptr_t *result)
481 {
482
483 switch (which) {
484 case PCIB_IVAR_DOMAIN:
485 *result = 0;
486 return 0;
487 case PCIB_IVAR_BUS:
488 *result = legacy_get_pcibus(dev);
489 return 0;
490 }
491 return ENOENT;
492 }
493
494 int
legacy_pcib_write_ivar(device_t dev,device_t child,int which,uintptr_t value)495 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
496 uintptr_t value)
497 {
498
499 switch (which) {
500 case PCIB_IVAR_DOMAIN:
501 return EINVAL;
502 case PCIB_IVAR_BUS:
503 legacy_set_pcibus(dev, value);
504 return 0;
505 }
506 return ENOENT;
507 }
508
509 SYSCTL_DECL(_hw_pci);
510
511 static unsigned long legacy_host_mem_start = 0x80000000;
512 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
513 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RD,
514 &legacy_host_mem_start, 0x80000000,
515 "Limit the host bridge memory to being above this address.");
516
517 struct resource *
legacy_pcib_alloc_resource(device_t dev,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags,int cpuid)518 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
519 u_long start, u_long end, u_long count, u_int flags, int cpuid)
520 {
521 /*
522 * If no memory preference is given, use upper 32MB slot most
523 * bioses use for their memory window. Typically other bridges
524 * before us get in the way to assert their preferences on memory.
525 * Hardcoding like this sucks, so a more MD/MI way needs to be
526 * found to do it. This is typically only used on older laptops
527 * that don't have pci busses behind pci bridge, so assuming > 32MB
528 * is liekly OK.
529 *
530 * However, this can cause problems for other chipsets, so we make
531 * this tunable by hw.pci.host_mem_start.
532 */
533 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
534 start = legacy_host_mem_start;
535 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
536 start = 0x1000;
537 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
538 count, flags, cpuid));
539 }
540
541 static device_method_t legacy_pcib_methods[] = {
542 /* Device interface */
543 DEVMETHOD(device_identify, legacy_pcib_identify),
544 DEVMETHOD(device_probe, legacy_pcib_probe),
545 DEVMETHOD(device_attach, legacy_pcib_attach),
546 DEVMETHOD(device_shutdown, bus_generic_shutdown),
547 DEVMETHOD(device_suspend, bus_generic_suspend),
548 DEVMETHOD(device_resume, bus_generic_resume),
549
550 /* Bus interface */
551 DEVMETHOD(bus_print_child, bus_generic_print_child),
552 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
553 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
554 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
555 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
556 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
557 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
558 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
559 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
560
561 /* pcib interface */
562 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
563 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
564 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
565 #ifdef notyet
566 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
567 #else
568 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt),
569 #endif
570 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
571 DEVMETHOD(pcib_release_msi, pcib_release_msi),
572 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
573 DEVMETHOD(pcib_release_msix, pcib_release_msix),
574 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
575 DEVMETHOD_END
576 };
577
578 static devclass_t hostb_devclass;
579
580 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
581 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, NULL, NULL);
582
583
584 /*
585 * Install placeholder to claim the resources owned by the
586 * PCI bus interface. This could be used to extract the
587 * config space registers in the extreme case where the PnP
588 * ID is available and the PCI BIOS isn't, but for now we just
589 * eat the PnP ID and do nothing else.
590 *
591 * XXX we should silence this probe, as it will generally confuse
592 * people.
593 */
594 static struct isa_pnp_id pcibus_pnp_ids[] = {
595 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
596 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
597 { 0 }
598 };
599
600 static int
pcibus_pnp_probe(device_t dev)601 pcibus_pnp_probe(device_t dev)
602 {
603 int result;
604
605 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
606 device_quiet(dev);
607 return(result);
608 }
609
610 static int
pcibus_pnp_attach(device_t dev)611 pcibus_pnp_attach(device_t dev)
612 {
613 return(0);
614 }
615
616 static device_method_t pcibus_pnp_methods[] = {
617 /* Device interface */
618 DEVMETHOD(device_probe, pcibus_pnp_probe),
619 DEVMETHOD(device_attach, pcibus_pnp_attach),
620 DEVMETHOD(device_detach, bus_generic_detach),
621 DEVMETHOD(device_shutdown, bus_generic_shutdown),
622 DEVMETHOD(device_suspend, bus_generic_suspend),
623 DEVMETHOD(device_resume, bus_generic_resume),
624 DEVMETHOD_END
625 };
626
627 static devclass_t pcibus_pnp_devclass;
628
629 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
630 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, NULL, NULL);
631
632
633 #ifdef notyet
634
635 /*
636 * Provide a PCI-PCI bridge driver for PCI busses behind PCI-PCI bridges
637 * that appear in the PCIBIOS Interrupt Routing Table to use the routing
638 * table for interrupt routing when possible.
639 */
640 static int pcibios_pcib_probe(device_t bus);
641
642 static device_method_t pcibios_pcib_pci_methods[] = {
643 /* Device interface */
644 DEVMETHOD(device_probe, pcibios_pcib_probe),
645 DEVMETHOD(device_attach, pcib_attach),
646 DEVMETHOD(device_shutdown, bus_generic_shutdown),
647 DEVMETHOD(device_suspend, bus_generic_suspend),
648 DEVMETHOD(device_resume, bus_generic_resume),
649
650 /* Bus interface */
651 DEVMETHOD(bus_print_child, bus_generic_print_child),
652 DEVMETHOD(bus_read_ivar, pcib_read_ivar),
653 DEVMETHOD(bus_write_ivar, pcib_write_ivar),
654 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource),
655 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
656 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
657 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
658 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
659 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
660
661 /* pcib interface */
662 DEVMETHOD(pcib_maxslots, pcib_maxslots),
663 DEVMETHOD(pcib_read_config, pcib_read_config),
664 DEVMETHOD(pcib_write_config, pcib_write_config),
665 DEVMETHOD(pcib_route_interrupt, pcibios_pcib_route_interrupt),
666 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi),
667 DEVMETHOD(pcib_release_msi, pcib_release_msi),
668 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix),
669 DEVMETHOD(pcib_release_msix, pcib_release_msix),
670 DEVMETHOD(pcib_map_msi, pcib_map_msi),
671
672 DEVMETHOD_END
673 };
674
675 static devclass_t pcib_devclass;
676
677 DEFINE_CLASS_0(pcib, pcibios_pcib_driver, pcibios_pcib_pci_methods,
678 sizeof(struct pcib_softc));
679 DRIVER_MODULE(pcibios_pcib, pci, pcibios_pcib_driver, pcib_devclass, NULL, NULL);
680
681 static int
pcibios_pcib_probe(device_t dev)682 pcibios_pcib_probe(device_t dev)
683 {
684 int bus;
685
686 if ((pci_get_class(dev) != PCIC_BRIDGE) ||
687 (pci_get_subclass(dev) != PCIS_BRIDGE_PCI))
688 return (ENXIO);
689 bus = pci_read_config(dev, PCIR_SECBUS_1, 1);
690 if (bus == 0)
691 return (ENXIO);
692 if (!pci_pir_probe(bus, 1))
693 return (ENXIO);
694 device_set_desc(dev, "PCIBIOS PCI-PCI bridge");
695 return (-2000);
696 }
697
698 static int
pcibios_pcib_route_interrupt(device_t pcib,device_t dev,int pin)699 pcibios_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
700 {
701 return (pci_pir_route_interrupt(pci_get_bus(dev), pci_get_slot(dev),
702 pci_get_function(dev), pin));
703 }
704
705 #endif /* notyet */
706