1 /*-
2 * Copyright (c) 1999, 2000 Matthew R. Green
3 * Copyright (c) 2001 - 2003 by Thomas Moestl <tmm@FreeBSD.org>
4 * Copyright (c) 2005 - 2006 Marius Strobl <marius@FreeBSD.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The name of the author may not be used to endorse or promote products
16 * derived from this software without specific prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * from: NetBSD: psycho.c,v 1.39 2001/10/07 20:30:41 eeh Exp
31 */
32
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35
36 /*
37 * Support for `Hummingbird' (UltraSPARC IIe), `Psycho' and `Psycho+'
38 * (UltraSPARC II) and `Sabre' (UltraSPARC IIi) UPA to PCI bridges.
39 */
40
41 #include "opt_ofw_pci.h"
42 #include "opt_psycho.h"
43
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/bus.h>
47 #include <sys/endian.h>
48 #include <sys/kdb.h>
49 #include <sys/kernel.h>
50 #include <sys/lock.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/mutex.h>
54 #include <sys/pcpu.h>
55 #include <sys/reboot.h>
56 #include <sys/rman.h>
57 #include <sys/sysctl.h>
58
59 #include <dev/ofw/ofw_bus.h>
60 #include <dev/ofw/openfirm.h>
61
62 #include <machine/bus.h>
63 #include <machine/bus_common.h>
64 #include <machine/bus_private.h>
65 #include <machine/iommureg.h>
66 #include <machine/iommuvar.h>
67 #include <machine/resource.h>
68 #include <machine/ver.h>
69
70 #include <dev/pci/pcireg.h>
71 #include <dev/pci/pcivar.h>
72
73 #include <sparc64/pci/ofw_pci.h>
74 #include <sparc64/pci/psychoreg.h>
75 #include <sparc64/pci/psychovar.h>
76
77 #include "pcib_if.h"
78
79 static const struct psycho_desc *psycho_find_desc(const struct psycho_desc *,
80 const char *);
81 static const struct psycho_desc *psycho_get_desc(device_t);
82 static void psycho_set_intr(struct psycho_softc *, u_int, bus_addr_t,
83 driver_filter_t, driver_intr_t);
84 static int psycho_find_intrmap(struct psycho_softc *, u_int, bus_addr_t *,
85 bus_addr_t *, u_long *);
86 static void sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map,
87 bus_dmasync_op_t op);
88 static void psycho_intr_enable(void *);
89 static void psycho_intr_disable(void *);
90 static void psycho_intr_assign(void *);
91 static void psycho_intr_clear(void *);
92
93 /* Interrupt handlers */
94 static driver_filter_t psycho_ue;
95 static driver_filter_t psycho_ce;
96 static driver_filter_t psycho_pci_bus;
97 static driver_filter_t psycho_powerdebug;
98 static driver_intr_t psycho_powerdown;
99 static driver_intr_t psycho_overtemp;
100 #ifdef PSYCHO_MAP_WAKEUP
101 static driver_filter_t psycho_wakeup;
102 #endif
103
104 /* IOMMU support */
105 static void psycho_iommu_init(struct psycho_softc *, int, uint32_t);
106
107 /*
108 * Methods
109 */
110 static device_probe_t psycho_probe;
111 static device_attach_t psycho_attach;
112 static bus_setup_intr_t psycho_setup_intr;
113 static bus_alloc_resource_t psycho_alloc_resource;
114 static pcib_maxslots_t psycho_maxslots;
115 static pcib_read_config_t psycho_read_config;
116 static pcib_write_config_t psycho_write_config;
117 static pcib_route_interrupt_t psycho_route_interrupt;
118 static ofw_pci_setup_device_t psycho_setup_device;
119
120 static device_method_t psycho_methods[] = {
121 /* Device interface */
122 DEVMETHOD(device_probe, psycho_probe),
123 DEVMETHOD(device_attach, psycho_attach),
124 DEVMETHOD(device_shutdown, bus_generic_shutdown),
125 DEVMETHOD(device_suspend, bus_generic_suspend),
126 DEVMETHOD(device_resume, bus_generic_resume),
127
128 /* Bus interface */
129 DEVMETHOD(bus_read_ivar, ofw_pci_read_ivar),
130 DEVMETHOD(bus_setup_intr, psycho_setup_intr),
131 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
132 DEVMETHOD(bus_alloc_resource, psycho_alloc_resource),
133 DEVMETHOD(bus_activate_resource, ofw_pci_activate_resource),
134 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
135 DEVMETHOD(bus_adjust_resource, ofw_pci_adjust_resource),
136 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
137 DEVMETHOD(bus_get_dma_tag, ofw_pci_get_dma_tag),
138
139 /* pcib interface */
140 DEVMETHOD(pcib_maxslots, psycho_maxslots),
141 DEVMETHOD(pcib_read_config, psycho_read_config),
142 DEVMETHOD(pcib_write_config, psycho_write_config),
143 DEVMETHOD(pcib_route_interrupt, psycho_route_interrupt),
144
145 /* ofw_bus interface */
146 DEVMETHOD(ofw_bus_get_node, ofw_pci_get_node),
147
148 /* ofw_pci interface */
149 DEVMETHOD(ofw_pci_setup_device, psycho_setup_device),
150
151 DEVMETHOD_END
152 };
153
154 static devclass_t psycho_devclass;
155
156 DEFINE_CLASS_0(pcib, psycho_driver, psycho_methods,
157 sizeof(struct psycho_softc));
158 EARLY_DRIVER_MODULE(psycho, nexus, psycho_driver, psycho_devclass, NULL, NULL,
159 BUS_PASS_BUS);
160
161 static SYSCTL_NODE(_hw, OID_AUTO, psycho, CTLFLAG_RD, 0, "psycho parameters");
162
163 static u_int psycho_powerfail = 1;
164 SYSCTL_UINT(_hw_psycho, OID_AUTO, powerfail, CTLFLAG_RDTUN, &psycho_powerfail,
165 0, "powerfail action (0: none, 1: shutdown (default), 2: debugger)");
166
167 static SLIST_HEAD(, psycho_softc) psycho_softcs =
168 SLIST_HEAD_INITIALIZER(psycho_softcs);
169
170 static const struct intr_controller psycho_ic = {
171 psycho_intr_enable,
172 psycho_intr_disable,
173 psycho_intr_assign,
174 psycho_intr_clear
175 };
176
177 struct psycho_icarg {
178 struct psycho_softc *pica_sc;
179 bus_addr_t pica_map;
180 bus_addr_t pica_clr;
181 };
182
183 #define PSYCHO_READ8(sc, off) \
184 bus_read_8((sc)->sc_mem_res, (off))
185 #define PSYCHO_WRITE8(sc, off, v) \
186 bus_write_8((sc)->sc_mem_res, (off), (v))
187 #define PCICTL_READ8(sc, off) \
188 PSYCHO_READ8((sc), (sc)->sc_pcictl + (off))
189 #define PCICTL_WRITE8(sc, off, v) \
190 PSYCHO_WRITE8((sc), (sc)->sc_pcictl + (off), (v))
191
192 /*
193 * "Sabre" is the UltraSPARC IIi onboard UPA to PCI bridge. It manages a
194 * single PCI bus and does not have a streaming buffer. It often has an APB
195 * (advanced PCI bridge) connected to it, which was designed specifically for
196 * the IIi. The APB lets the IIi handle two independent PCI buses, and
197 * appears as two "Simba"'s underneath the Sabre.
198 *
199 * "Hummingbird" is the UltraSPARC IIe onboard UPA to PCI bridge. It's
200 * basically the same as Sabre but without an APB underneath it.
201 *
202 * "Psycho" and "Psycho+" are dual UPA to PCI bridges. They sit on the UPA
203 * bus and manage two PCI buses. "Psycho" has two 64-bit 33MHz buses, while
204 * "Psycho+" controls both a 64-bit 33Mhz and a 64-bit 66Mhz PCI bus. You
205 * will usually find a "Psycho+" since I don't think the original "Psycho"
206 * ever shipped, and if it did it would be in the U30.
207 *
208 * Each "Psycho" PCI bus appears as a separate OFW node, but since they are
209 * both part of the same IC, they only have a single register space. As such,
210 * they need to be configured together, even though the autoconfiguration will
211 * attach them separately.
212 *
213 * On UltraIIi machines, "Sabre" itself usually takes pci0, with "Simba" often
214 * as pci1 and pci2, although they have been implemented with other PCI bus
215 * numbers on some machines.
216 *
217 * On UltraII machines, there can be any number of "Psycho+" ICs, each
218 * providing two PCI buses.
219 */
220
221 struct psycho_desc {
222 const char *pd_string;
223 int pd_mode;
224 const char *pd_name;
225 };
226
227 static const struct psycho_desc psycho_compats[] = {
228 { "pci108e,8000", PSYCHO_MODE_PSYCHO, "Psycho compatible" },
229 { "pci108e,a000", PSYCHO_MODE_SABRE, "Sabre compatible" },
230 { "pci108e,a001", PSYCHO_MODE_SABRE, "Hummingbird compatible" },
231 { NULL, 0, NULL }
232 };
233
234 static const struct psycho_desc psycho_models[] = {
235 { "SUNW,psycho", PSYCHO_MODE_PSYCHO, "Psycho" },
236 { "SUNW,sabre", PSYCHO_MODE_SABRE, "Sabre" },
237 { NULL, 0, NULL }
238 };
239
240 static const struct psycho_desc *
psycho_find_desc(const struct psycho_desc * table,const char * string)241 psycho_find_desc(const struct psycho_desc *table, const char *string)
242 {
243 const struct psycho_desc *desc;
244
245 if (string == NULL)
246 return (NULL);
247 for (desc = table; desc->pd_string != NULL; desc++)
248 if (strcmp(desc->pd_string, string) == 0)
249 return (desc);
250 return (NULL);
251 }
252
253 static const struct psycho_desc *
psycho_get_desc(device_t dev)254 psycho_get_desc(device_t dev)
255 {
256 const struct psycho_desc *rv;
257
258 rv = psycho_find_desc(psycho_models, ofw_bus_get_model(dev));
259 if (rv == NULL)
260 rv = psycho_find_desc(psycho_compats,
261 ofw_bus_get_compat(dev));
262 return (rv);
263 }
264
265 static int
psycho_probe(device_t dev)266 psycho_probe(device_t dev)
267 {
268 const char *dtype;
269
270 dtype = ofw_bus_get_type(dev);
271 if (dtype != NULL && strcmp(dtype, OFW_TYPE_PCI) == 0 &&
272 psycho_get_desc(dev) != NULL) {
273 device_set_desc(dev, "U2P UPA-PCI bridge");
274 return (0);
275 }
276 return (ENXIO);
277 }
278
279 static int
psycho_attach(device_t dev)280 psycho_attach(device_t dev)
281 {
282 struct psycho_icarg *pica;
283 struct psycho_softc *asc, *sc, *osc;
284 const struct psycho_desc *desc;
285 bus_addr_t intrclr, intrmap;
286 bus_dma_tag_t dmat;
287 uint64_t csr, dr;
288 phandle_t node;
289 uint32_t dvmabase, prop;
290 u_int rerun, ver;
291 int i, j;
292
293 node = ofw_bus_get_node(dev);
294 sc = device_get_softc(dev);
295 desc = psycho_get_desc(dev);
296
297 sc->sc_dev = dev;
298 sc->sc_mode = desc->pd_mode;
299
300 /*
301 * The Psycho gets three register banks:
302 * (0) per-PBM configuration and status registers
303 * (1) per-PBM PCI configuration space, containing only the
304 * PBM 256-byte PCI header
305 * (2) the shared Psycho configuration registers
306 */
307 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
308 i = 2;
309 sc->sc_pcictl =
310 bus_get_resource_start(dev, SYS_RES_MEMORY, 0) -
311 bus_get_resource_start(dev, SYS_RES_MEMORY, 2);
312 switch (sc->sc_pcictl) {
313 case PSR_PCICTL0:
314 sc->sc_half = 0;
315 break;
316 case PSR_PCICTL1:
317 sc->sc_half = 1;
318 break;
319 default:
320 panic("%s: bogus PCI control register location",
321 __func__);
322 /* NOTREACHED */
323 }
324 } else {
325 i = 0;
326 sc->sc_pcictl = PSR_PCICTL0;
327 sc->sc_half = 0;
328 }
329 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
330 (sc->sc_mode == PSYCHO_MODE_PSYCHO ? RF_SHAREABLE : 0) |
331 RF_ACTIVE);
332 if (sc->sc_mem_res == NULL)
333 panic("%s: could not allocate registers", __func__);
334
335 /*
336 * Match other Psychos that are already configured against
337 * the base physical address. This will be the same for a
338 * pair of devices that share register space.
339 */
340 osc = NULL;
341 SLIST_FOREACH(asc, &psycho_softcs, sc_link) {
342 if (rman_get_start(asc->sc_mem_res) ==
343 rman_get_start(sc->sc_mem_res)) {
344 /* Found partner. */
345 osc = asc;
346 break;
347 }
348 }
349 if (osc == NULL) {
350 sc->sc_mtx = malloc(sizeof(*sc->sc_mtx), M_DEVBUF,
351 M_NOWAIT | M_ZERO);
352 if (sc->sc_mtx == NULL)
353 panic("%s: could not malloc mutex", __func__);
354 mtx_init(sc->sc_mtx, "pcib_mtx", NULL, MTX_SPIN);
355 } else {
356 if (sc->sc_mode != PSYCHO_MODE_PSYCHO)
357 panic("%s: no partner expected", __func__);
358 if (mtx_initialized(osc->sc_mtx) == 0)
359 panic("%s: mutex not initialized", __func__);
360 sc->sc_mtx = osc->sc_mtx;
361 }
362 SLIST_INSERT_HEAD(&psycho_softcs, sc, sc_link);
363
364 csr = PSYCHO_READ8(sc, PSR_CS);
365 ver = PSYCHO_GCSR_VERS(csr);
366 sc->sc_ign = 0x1f; /* Hummingbird/Sabre IGN is always 0x1f. */
367 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
368 sc->sc_ign = PSYCHO_GCSR_IGN(csr);
369 if (OF_getprop(node, "clock-frequency", &prop, sizeof(prop)) == -1)
370 prop = 33000000;
371
372 device_printf(dev,
373 "%s, impl %d, version %d, IGN %#x, bus %c, %dMHz\n",
374 desc->pd_name, (u_int)PSYCHO_GCSR_IMPL(csr), ver, sc->sc_ign,
375 'A' + sc->sc_half, prop / 1000 / 1000);
376
377 /* Set up the PCI control and PCI diagnostic registers. */
378
379 csr = PCICTL_READ8(sc, PCR_CS);
380 csr &= ~PCICTL_ARB_PARK;
381 if (OF_getproplen(node, "no-bus-parking") < 0)
382 csr |= PCICTL_ARB_PARK;
383
384 /* Workarounds for version specific bugs. */
385 dr = PCICTL_READ8(sc, PCR_DIAG);
386 switch (ver) {
387 case 0:
388 dr |= DIAG_RTRY_DIS;
389 dr &= ~DIAG_DWSYNC_DIS;
390 rerun = 0;
391 break;
392 case 1:
393 csr &= ~PCICTL_ARB_PARK;
394 dr |= DIAG_RTRY_DIS | DIAG_DWSYNC_DIS;
395 rerun = 0;
396 break;
397 default:
398 dr |= DIAG_DWSYNC_DIS;
399 dr &= ~DIAG_RTRY_DIS;
400 rerun = 1;
401 break;
402 }
403
404 csr |= PCICTL_ERRINTEN | PCICTL_ARB_4;
405 csr &= ~(PCICTL_SBHINTEN | PCICTL_WAKEUPEN);
406 #ifdef PSYCHO_DEBUG
407 device_printf(dev, "PCI CSR 0x%016llx -> 0x%016llx\n",
408 (unsigned long long)PCICTL_READ8(sc, PCR_CS),
409 (unsigned long long)csr);
410 #endif
411 PCICTL_WRITE8(sc, PCR_CS, csr);
412
413 dr &= ~DIAG_ISYNC_DIS;
414 #ifdef PSYCHO_DEBUG
415 device_printf(dev, "PCI DR 0x%016llx -> 0x%016llx\n",
416 (unsigned long long)PCICTL_READ8(sc, PCR_DIAG),
417 (unsigned long long)dr);
418 #endif
419 PCICTL_WRITE8(sc, PCR_DIAG, dr);
420
421 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
422 /* Use the PROM preset for now. */
423 csr = PCICTL_READ8(sc, PCR_TAS);
424 if (csr == 0)
425 panic("%s: Hummingbird/Sabre TAS not initialized.",
426 __func__);
427 dvmabase = (ffs(csr) - 1) << PCITAS_ADDR_SHIFT;
428 } else
429 dvmabase = -1;
430
431 /*
432 * If we're a Hummingbird/Sabre or the first of a pair of Psychos
433 * to arrive here, do the interrupt setup and start up the IOMMU.
434 */
435 if (osc == NULL) {
436 /*
437 * Hunt through all the interrupt mapping regs and register
438 * our interrupt controller for the corresponding interrupt
439 * vectors. We do this early in order to be able to catch
440 * stray interrupts.
441 */
442 for (i = 0; i <= PSYCHO_MAX_INO; i++) {
443 if (psycho_find_intrmap(sc, i, &intrmap, &intrclr,
444 NULL) == 0)
445 continue;
446 pica = malloc(sizeof(*pica), M_DEVBUF, M_NOWAIT);
447 if (pica == NULL)
448 panic("%s: could not allocate interrupt "
449 "controller argument", __func__);
450 pica->pica_sc = sc;
451 pica->pica_map = intrmap;
452 pica->pica_clr = intrclr;
453 #ifdef PSYCHO_DEBUG
454 /*
455 * Enable all interrupts and clear all interrupt
456 * states. This aids the debugging of interrupt
457 * routing problems.
458 */
459 device_printf(dev,
460 "intr map (INO %d, %s) %#lx: %#lx, clr: %#lx\n",
461 i, intrmap <= PSR_PCIB3_INT_MAP ? "PCI" : "OBIO",
462 (u_long)intrmap, (u_long)PSYCHO_READ8(sc,
463 intrmap), (u_long)intrclr);
464 PSYCHO_WRITE8(sc, intrmap, INTMAP_VEC(sc->sc_ign, i));
465 PSYCHO_WRITE8(sc, intrclr, INTCLR_IDLE);
466 PSYCHO_WRITE8(sc, intrmap,
467 INTMAP_ENABLE(INTMAP_VEC(sc->sc_ign, i),
468 PCPU_GET(mid)));
469 #endif
470 j = intr_controller_register(INTMAP_VEC(sc->sc_ign,
471 i), &psycho_ic, pica);
472 if (j != 0)
473 device_printf(dev, "could not register "
474 "interrupt controller for INO %d (%d)\n",
475 i, j);
476 }
477
478 if (sc->sc_mode == PSYCHO_MODE_PSYCHO)
479 sparc64_counter_init(device_get_nameunit(dev),
480 rman_get_bustag(sc->sc_mem_res),
481 rman_get_bushandle(sc->sc_mem_res), PSR_TC0);
482
483 /*
484 * Set up IOMMU and PCI configuration if we're the first
485 * of a pair of Psychos to arrive here or a Hummingbird
486 * or Sabre.
487 *
488 * We should calculate a TSB size based on amount of RAM
489 * and number of bus controllers and number and type of
490 * child devices.
491 *
492 * For the moment, 32KB should be more than enough.
493 */
494 sc->sc_is = malloc(sizeof(*sc->sc_is), M_DEVBUF, M_NOWAIT |
495 M_ZERO);
496 if (sc->sc_is == NULL)
497 panic("%s: could not malloc IOMMU state", __func__);
498 sc->sc_is->is_flags = IOMMU_PRESERVE_PROM;
499 if (sc->sc_mode == PSYCHO_MODE_SABRE) {
500 sc->sc_dma_methods =
501 malloc(sizeof(*sc->sc_dma_methods), M_DEVBUF,
502 M_NOWAIT);
503 if (sc->sc_dma_methods == NULL)
504 panic("%s: could not malloc DMA methods",
505 __func__);
506 memcpy(sc->sc_dma_methods, &iommu_dma_methods,
507 sizeof(*sc->sc_dma_methods));
508 sc->sc_dma_methods->dm_dmamap_sync =
509 sabre_dmamap_sync;
510 sc->sc_is->is_pmaxaddr =
511 IOMMU_MAXADDR(SABRE_IOMMU_BITS);
512 } else {
513 sc->sc_dma_methods = &iommu_dma_methods;
514 sc->sc_is->is_pmaxaddr =
515 IOMMU_MAXADDR(PSYCHO_IOMMU_BITS);
516 }
517 sc->sc_is->is_sb[0] = sc->sc_is->is_sb[1] = 0;
518 if (OF_getproplen(node, "no-streaming-cache") < 0)
519 sc->sc_is->is_sb[0] = sc->sc_pcictl + PCR_STRBUF;
520 sc->sc_is->is_flags |= (rerun != 1) ? IOMMU_RERUN_DISABLE : 0;
521 psycho_iommu_init(sc, 3, dvmabase);
522 } else {
523 /* Just copy IOMMU state, config tag and address. */
524 sc->sc_dma_methods = &iommu_dma_methods;
525 sc->sc_is = osc->sc_is;
526 if (OF_getproplen(node, "no-streaming-cache") < 0)
527 sc->sc_is->is_sb[1] = sc->sc_pcictl + PCR_STRBUF;
528 iommu_reset(sc->sc_is);
529 }
530
531 /* Create our DMA tag. */
532 if (bus_dma_tag_create(bus_get_dma_tag(dev), 8, 0,
533 sc->sc_is->is_pmaxaddr, ~0, NULL, NULL, sc->sc_is->is_pmaxaddr,
534 0xff, 0xffffffff, 0, NULL, NULL, &dmat) != 0)
535 panic("%s: could not create PCI DMA tag", __func__);
536 dmat->dt_cookie = sc->sc_is;
537 dmat->dt_mt = sc->sc_dma_methods;
538
539 if (ofw_pci_attach_common(dev, dmat, PSYCHO_IO_SIZE,
540 PSYCHO_MEM_SIZE) != 0)
541 panic("%s: ofw_pci_attach_common() failed", __func__);
542
543 /* Clear any pending PCI error bits. */
544 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
545 PCIR_STATUS, PCIB_READ_CONFIG(dev, sc->sc_ops.sc_pci_secbus,
546 PCS_DEVICE, PCS_FUNC, PCIR_STATUS, 2), 2);
547 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS));
548 PCICTL_WRITE8(sc, PCR_AFS, PCICTL_READ8(sc, PCR_AFS));
549
550 if (osc == NULL) {
551 /*
552 * Establish handlers for interesting interrupts...
553 *
554 * XXX We need to remember these and remove this to support
555 * hotplug on the UPA/FHC bus.
556 *
557 * XXX Not all controllers have these, but installing them
558 * is better than trying to sort through this mess.
559 */
560 psycho_set_intr(sc, 1, PSR_UE_INT_MAP, psycho_ue, NULL);
561 psycho_set_intr(sc, 2, PSR_CE_INT_MAP, psycho_ce, NULL);
562 switch (psycho_powerfail) {
563 case 0:
564 break;
565 case 2:
566 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP,
567 psycho_powerdebug, NULL);
568 break;
569 default:
570 psycho_set_intr(sc, 3, PSR_POWER_INT_MAP, NULL,
571 psycho_powerdown);
572 break;
573 }
574 if (sc->sc_mode == PSYCHO_MODE_PSYCHO) {
575 /*
576 * Hummingbirds/Sabres do not have the following two
577 * interrupts.
578 */
579
580 /*
581 * The spare hardware interrupt is used for the
582 * over-temperature interrupt.
583 */
584 psycho_set_intr(sc, 4, PSR_SPARE_INT_MAP, NULL,
585 psycho_overtemp);
586 #ifdef PSYCHO_MAP_WAKEUP
587 /*
588 * psycho_wakeup() doesn't do anything useful right
589 * now.
590 */
591 psycho_set_intr(sc, 5, PSR_PWRMGT_INT_MAP,
592 psycho_wakeup, NULL);
593 #endif /* PSYCHO_MAP_WAKEUP */
594 }
595 }
596 /*
597 * Register a PCI bus error interrupt handler according to which
598 * half this is. Hummingbird/Sabre don't have a PCI bus B error
599 * interrupt but they are also only used for PCI bus A.
600 */
601 psycho_set_intr(sc, 0, sc->sc_half == 0 ? PSR_PCIAERR_INT_MAP :
602 PSR_PCIBERR_INT_MAP, psycho_pci_bus, NULL);
603
604 /*
605 * Set the latency timer register as this isn't always done by the
606 * firmware.
607 */
608 PCIB_WRITE_CONFIG(dev, sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC,
609 PCIR_LATTIMER, OFW_PCI_LATENCY, 1);
610
611 for (i = PCIR_VENDOR; i < PCIR_STATUS; i += sizeof(uint16_t))
612 le16enc(&sc->sc_pci_hpbcfg[i],
613 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
614 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
615 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus, PCS_DEVICE,
616 PCS_FUNC, i)));
617 for (i = PCIR_REVID; i <= PCIR_BIST; i += sizeof(uint8_t))
618 sc->sc_pci_hpbcfg[i] = bus_space_read_1(sc->sc_ops.sc_pci_cfgt,
619 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG], PSYCHO_CONF_OFF(
620 sc->sc_ops.sc_pci_secbus, PCS_DEVICE, PCS_FUNC, i));
621
622 /*
623 * On E250 the interrupt map entry for the EBus bridge is wrong,
624 * causing incorrect interrupts to be assigned to some devices on
625 * the EBus. Work around it by changing our copy of the interrupt
626 * map mask to perform a full comparison of the INO. That way
627 * the interrupt map entry for the EBus bridge won't match at all
628 * and the INOs specified in the "interrupts" properties of the
629 * EBus devices will be used directly instead.
630 */
631 if (strcmp(sparc64_model, "SUNW,Ultra-250") == 0 &&
632 sc->sc_ops.sc_pci_iinfo.opi_imapmsk != NULL)
633 *(ofw_pci_intr_t *)(&sc->sc_ops.sc_pci_iinfo.opi_imapmsk[
634 sc->sc_ops.sc_pci_iinfo.opi_addrc]) = INTMAP_INO_MASK;
635
636 device_add_child(dev, "pci", -1);
637 return (bus_generic_attach(dev));
638 }
639
640 static void
psycho_set_intr(struct psycho_softc * sc,u_int index,bus_addr_t intrmap,driver_filter_t filt,driver_intr_t intr)641 psycho_set_intr(struct psycho_softc *sc, u_int index, bus_addr_t intrmap,
642 driver_filter_t filt, driver_intr_t intr)
643 {
644 u_long vec;
645 int rid;
646
647 rid = index;
648 sc->sc_irq_res[index] = bus_alloc_resource_any(sc->sc_dev,
649 SYS_RES_IRQ, &rid, RF_ACTIVE);
650 if (sc->sc_irq_res[index] == NULL && intrmap >= PSR_POWER_INT_MAP) {
651 /*
652 * These interrupts aren't mandatory and not available
653 * with all controllers (not even Psychos).
654 */
655 return;
656 }
657 if (sc->sc_irq_res[index] == NULL ||
658 INTIGN(vec = rman_get_start(sc->sc_irq_res[index])) !=
659 sc->sc_ign ||
660 INTVEC(PSYCHO_READ8(sc, intrmap)) != vec ||
661 intr_vectors[vec].iv_ic != &psycho_ic ||
662 bus_setup_intr(sc->sc_dev, sc->sc_irq_res[index],
663 INTR_TYPE_MISC | INTR_BRIDGE, filt, intr, sc,
664 &sc->sc_ihand[index]) != 0)
665 panic("%s: failed to set up interrupt %d", __func__, index);
666 }
667
668 static int
psycho_find_intrmap(struct psycho_softc * sc,u_int ino,bus_addr_t * intrmapptr,bus_addr_t * intrclrptr,bus_addr_t * intrdiagptr)669 psycho_find_intrmap(struct psycho_softc *sc, u_int ino,
670 bus_addr_t *intrmapptr, bus_addr_t *intrclrptr, bus_addr_t *intrdiagptr)
671 {
672 bus_addr_t intrclr, intrmap;
673 uint64_t diag;
674 int found;
675
676 /*
677 * XXX we only compare INOs rather than INRs since the firmware may
678 * not provide the IGN and the IGN is constant for all devices on
679 * that PCI controller.
680 * This could cause problems for the FFB/external interrupt which
681 * has a full vector that can be set arbitrarily.
682 */
683
684 if (ino > PSYCHO_MAX_INO) {
685 device_printf(sc->sc_dev, "out of range INO %d requested\n",
686 ino);
687 return (0);
688 }
689
690 found = 0;
691 /* Hunt through OBIO first. */
692 diag = PSYCHO_READ8(sc, PSR_OBIO_INT_DIAG);
693 for (intrmap = PSR_SCSI_INT_MAP, intrclr = PSR_SCSI_INT_CLR;
694 intrmap <= PSR_PWRMGT_INT_MAP; intrmap += 8, intrclr += 8,
695 diag >>= 2) {
696 if (sc->sc_mode == PSYCHO_MODE_SABRE &&
697 (intrmap == PSR_TIMER0_INT_MAP ||
698 intrmap == PSR_TIMER1_INT_MAP ||
699 intrmap == PSR_PCIBERR_INT_MAP ||
700 intrmap == PSR_PWRMGT_INT_MAP))
701 continue;
702 if (INTINO(PSYCHO_READ8(sc, intrmap)) == ino) {
703 diag &= 2;
704 found = 1;
705 break;
706 }
707 }
708
709 if (!found) {
710 diag = PSYCHO_READ8(sc, PSR_PCI_INT_DIAG);
711 /* Now do PCI interrupts. */
712 for (intrmap = PSR_PCIA0_INT_MAP, intrclr = PSR_PCIA0_INT_CLR;
713 intrmap <= PSR_PCIB3_INT_MAP; intrmap += 8, intrclr += 32,
714 diag >>= 8) {
715 if (sc->sc_mode == PSYCHO_MODE_PSYCHO &&
716 (intrmap == PSR_PCIA2_INT_MAP ||
717 intrmap == PSR_PCIA3_INT_MAP))
718 continue;
719 if (((PSYCHO_READ8(sc, intrmap) ^ ino) & 0x3c) == 0) {
720 intrclr += 8 * (ino & 3);
721 diag = (diag >> ((ino & 3) * 2)) & 2;
722 found = 1;
723 break;
724 }
725 }
726 }
727 if (intrmapptr != NULL)
728 *intrmapptr = intrmap;
729 if (intrclrptr != NULL)
730 *intrclrptr = intrclr;
731 if (intrdiagptr != NULL)
732 *intrdiagptr = diag;
733 return (found);
734 }
735
736 /*
737 * Interrupt handlers
738 */
739 static int
psycho_ue(void * arg)740 psycho_ue(void *arg)
741 {
742 struct psycho_softc *sc = arg;
743 uint64_t afar, afsr;
744
745 afar = PSYCHO_READ8(sc, PSR_UE_AFA);
746 afsr = PSYCHO_READ8(sc, PSR_UE_AFS);
747 /*
748 * On the UltraSPARC-IIi/IIe, IOMMU misses/protection faults cause
749 * the AFAR to be set to the physical address of the TTE entry that
750 * was invalid/write protected. Call into the IOMMU code to have
751 * them decoded to virtual I/O addresses.
752 */
753 if ((afsr & UEAFSR_P_DTE) != 0)
754 iommu_decode_fault(sc->sc_is, afar);
755 panic("%s: uncorrectable DMA error AFAR %#lx AFSR %#lx",
756 device_get_nameunit(sc->sc_dev), (u_long)afar, (u_long)afsr);
757 return (FILTER_HANDLED);
758 }
759
760 static int
psycho_ce(void * arg)761 psycho_ce(void *arg)
762 {
763 struct psycho_softc *sc = arg;
764 uint64_t afar, afsr;
765
766 mtx_lock_spin(sc->sc_mtx);
767 afar = PSYCHO_READ8(sc, PSR_CE_AFA);
768 afsr = PSYCHO_READ8(sc, PSR_CE_AFS);
769 device_printf(sc->sc_dev, "correctable DMA error AFAR %#lx "
770 "AFSR %#lx\n", (u_long)afar, (u_long)afsr);
771 /* Clear the error bits that we caught. */
772 PSYCHO_WRITE8(sc, PSR_CE_AFS, afsr);
773 mtx_unlock_spin(sc->sc_mtx);
774 return (FILTER_HANDLED);
775 }
776
777 static int
psycho_pci_bus(void * arg)778 psycho_pci_bus(void *arg)
779 {
780 struct psycho_softc *sc = arg;
781 uint64_t afar, afsr;
782
783 afar = PCICTL_READ8(sc, PCR_AFA);
784 afsr = PCICTL_READ8(sc, PCR_AFS);
785 panic("%s: PCI bus %c error AFAR %#lx AFSR %#lx",
786 device_get_nameunit(sc->sc_dev), 'A' + sc->sc_half, (u_long)afar,
787 (u_long)afsr);
788 return (FILTER_HANDLED);
789 }
790
791 static int
psycho_powerdebug(void * arg __unused)792 psycho_powerdebug(void *arg __unused)
793 {
794
795 kdb_enter(KDB_WHY_POWERFAIL, "powerfail");
796 return (FILTER_HANDLED);
797 }
798
799 static void
psycho_powerdown(void * arg __unused)800 psycho_powerdown(void *arg __unused)
801 {
802 static int shutdown;
803
804 /* As the interrupt is cleared we may be called multiple times. */
805 if (shutdown != 0)
806 return;
807 shutdown++;
808 printf("Power Failure Detected: Shutting down NOW.\n");
809 shutdown_nice(RB_POWEROFF);
810 }
811
812 static void
psycho_overtemp(void * arg __unused)813 psycho_overtemp(void *arg __unused)
814 {
815 static int shutdown;
816
817 /* As the interrupt is cleared we may be called multiple times. */
818 if (shutdown != 0)
819 return;
820 shutdown++;
821 printf("DANGER: OVER TEMPERATURE detected.\nShutting down NOW.\n");
822 shutdown_nice(RB_POWEROFF);
823 }
824
825 #ifdef PSYCHO_MAP_WAKEUP
826 static int
psycho_wakeup(void * arg)827 psycho_wakeup(void *arg)
828 {
829 struct psycho_softc *sc = arg;
830
831 /* We don't really have a framework to deal with this properly. */
832 device_printf(sc->sc_dev, "power management wakeup\n");
833 return (FILTER_HANDLED);
834 }
835 #endif /* PSYCHO_MAP_WAKEUP */
836
837 static void
psycho_iommu_init(struct psycho_softc * sc,int tsbsize,uint32_t dvmabase)838 psycho_iommu_init(struct psycho_softc *sc, int tsbsize, uint32_t dvmabase)
839 {
840 struct iommu_state *is = sc->sc_is;
841
842 /* Punch in our copies. */
843 is->is_bustag = rman_get_bustag(sc->sc_mem_res);
844 is->is_bushandle = rman_get_bushandle(sc->sc_mem_res);
845 is->is_iommu = PSR_IOMMU;
846 is->is_dtag = PSR_IOMMU_TLB_TAG_DIAG;
847 is->is_ddram = PSR_IOMMU_TLB_DATA_DIAG;
848 is->is_dqueue = PSR_IOMMU_QUEUE_DIAG;
849 is->is_dva = PSR_IOMMU_SVADIAG;
850 is->is_dtcmp = PSR_IOMMU_TLB_CMP_DIAG;
851
852 iommu_init(device_get_nameunit(sc->sc_dev), is, tsbsize, dvmabase, 0);
853 }
854
855 static int
psycho_maxslots(device_t dev)856 psycho_maxslots(device_t dev)
857 {
858
859 /* XXX: is this correct? */
860 return (PCI_SLOTMAX);
861 }
862
863 static uint32_t
psycho_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)864 psycho_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
865 int width)
866 {
867 struct psycho_softc *sc;
868
869 sc = device_get_softc(dev);
870 /*
871 * The Hummingbird and Sabre bridges are picky in that they
872 * only allow their config space to be accessed using the
873 * "native" width of the respective register being accessed
874 * and return semi-random other content of their config space
875 * otherwise. Given that the PCI specs don't say anything
876 * about such a (unusual) limitation and lots of stuff expects
877 * to be able to access the contents of the config space at
878 * any width we allow just that. We do this by using a copy
879 * of the header of the bridge (the rest is all zero anyway)
880 * read during attach (expect for PCIR_STATUS) in order to
881 * simplify things.
882 * The Psycho bridges contain a dupe of their header at 0x80
883 * which we nullify that way also.
884 */
885 if (bus == sc->sc_ops.sc_pci_secbus && slot == PCS_DEVICE &&
886 func == PCS_FUNC) {
887 if (reg % width != 0)
888 return (-1);
889
890 if (reg >= sizeof(sc->sc_pci_hpbcfg))
891 return (0);
892
893 if ((reg < PCIR_STATUS && reg + width > PCIR_STATUS) ||
894 reg == PCIR_STATUS || reg == PCIR_STATUS + 1)
895 le16enc(&sc->sc_pci_hpbcfg[PCIR_STATUS],
896 bus_space_read_2(sc->sc_ops.sc_pci_cfgt,
897 sc->sc_ops.sc_pci_bh[OFW_PCI_CS_CONFIG],
898 PSYCHO_CONF_OFF(sc->sc_ops.sc_pci_secbus,
899 PCS_DEVICE, PCS_FUNC, PCIR_STATUS)));
900
901 switch (width) {
902 case 1:
903 return (sc->sc_pci_hpbcfg[reg]);
904 case 2:
905 return (le16dec(&sc->sc_pci_hpbcfg[reg]));
906 case 4:
907 return (le32dec(&sc->sc_pci_hpbcfg[reg]));
908 }
909 }
910
911 return (ofw_pci_read_config_common(dev, PCI_REGMAX,
912 PSYCHO_CONF_OFF(bus, slot, func, reg), bus, slot, func, reg,
913 width));
914 }
915
916 static void
psycho_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,uint32_t val,int width)917 psycho_write_config(device_t dev, u_int bus, u_int slot, u_int func,
918 u_int reg, uint32_t val, int width)
919 {
920
921 ofw_pci_write_config_common(dev, PCI_REGMAX, PSYCHO_CONF_OFF(bus,
922 slot, func, reg), bus, slot, func, reg, val, width);
923 }
924
925 static int
psycho_route_interrupt(device_t bridge,device_t dev,int pin)926 psycho_route_interrupt(device_t bridge, device_t dev, int pin)
927 {
928 struct psycho_softc *sc;
929 bus_addr_t intrmap;
930 ofw_pci_intr_t mintr;
931
932 mintr = ofw_pci_route_interrupt_common(bridge, dev, pin);
933 if (PCI_INTERRUPT_VALID(mintr))
934 return (mintr);
935 /*
936 * If this is outside of the range for an intpin, it's likely a full
937 * INO, and no mapping is required at all; this happens on the U30,
938 * where there's no interrupt map at the Psycho node. Fortunately,
939 * there seem to be no INOs in the intpin range on this boxen, so
940 * this easy heuristics will do.
941 */
942 if (pin > 4)
943 return (pin);
944 /*
945 * Guess the INO; we always assume that this is a non-OBIO
946 * device, and that pin is a "real" intpin number. Determine
947 * the mapping register to be used by the slot number.
948 * We only need to do this on E450s, it seems; here, the slot numbers
949 * for bus A are one-based, while those for bus B seemingly have an
950 * offset of 2 (hence the factor of 3 below).
951 */
952 sc = device_get_softc(dev);
953 intrmap = PSR_PCIA0_INT_MAP +
954 8 * (pci_get_slot(dev) - 1 + 3 * sc->sc_half);
955 mintr = INTINO(PSYCHO_READ8(sc, intrmap)) + pin - 1;
956 device_printf(bridge,
957 "guessing interrupt %d for device %d.%d pin %d\n",
958 (int)mintr, pci_get_slot(dev), pci_get_function(dev), pin);
959 return (mintr);
960 }
961
962 static void
sabre_dmamap_sync(bus_dma_tag_t dt,bus_dmamap_t map,bus_dmasync_op_t op)963 sabre_dmamap_sync(bus_dma_tag_t dt, bus_dmamap_t map, bus_dmasync_op_t op)
964 {
965 struct iommu_state *is = dt->dt_cookie;
966
967 if ((map->dm_flags & DMF_LOADED) == 0)
968 return;
969
970 if ((op & BUS_DMASYNC_POSTREAD) != 0)
971 (void)bus_space_read_8(is->is_bustag, is->is_bushandle,
972 PSR_DMA_WRITE_SYNC);
973
974 if ((op & BUS_DMASYNC_PREWRITE) != 0)
975 membar(Sync);
976 }
977
978 static void
psycho_intr_enable(void * arg)979 psycho_intr_enable(void *arg)
980 {
981 struct intr_vector *iv = arg;
982 struct psycho_icarg *pica = iv->iv_icarg;
983
984 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map,
985 INTMAP_ENABLE(iv->iv_vec, iv->iv_mid));
986 }
987
988 static void
psycho_intr_disable(void * arg)989 psycho_intr_disable(void *arg)
990 {
991 struct intr_vector *iv = arg;
992 struct psycho_icarg *pica = iv->iv_icarg;
993
994 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, iv->iv_vec);
995 }
996
997 static void
psycho_intr_assign(void * arg)998 psycho_intr_assign(void *arg)
999 {
1000 struct intr_vector *iv = arg;
1001 struct psycho_icarg *pica = iv->iv_icarg;
1002
1003 PSYCHO_WRITE8(pica->pica_sc, pica->pica_map, INTMAP_TID(
1004 PSYCHO_READ8(pica->pica_sc, pica->pica_map), iv->iv_mid));
1005 }
1006
1007 static void
psycho_intr_clear(void * arg)1008 psycho_intr_clear(void *arg)
1009 {
1010 struct intr_vector *iv = arg;
1011 struct psycho_icarg *pica = iv->iv_icarg;
1012
1013 PSYCHO_WRITE8(pica->pica_sc, pica->pica_clr, INTCLR_IDLE);
1014 }
1015
1016 static int
psycho_setup_intr(device_t dev,device_t child,struct resource * ires,int flags,driver_filter_t * filt,driver_intr_t * intr,void * arg,void ** cookiep)1017 psycho_setup_intr(device_t dev, device_t child, struct resource *ires,
1018 int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
1019 void **cookiep)
1020 {
1021 struct psycho_softc *sc;
1022 u_long vec;
1023
1024 sc = device_get_softc(dev);
1025 /*
1026 * Make sure the vector is fully specified and we registered
1027 * our interrupt controller for it.
1028 */
1029 vec = rman_get_start(ires);
1030 if (INTIGN(vec) != sc->sc_ign ||
1031 intr_vectors[vec].iv_ic != &psycho_ic) {
1032 device_printf(dev, "invalid interrupt vector 0x%lx\n", vec);
1033 return (EINVAL);
1034 }
1035 return (bus_generic_setup_intr(dev, child, ires, flags, filt, intr,
1036 arg, cookiep));
1037 }
1038
1039 static struct resource *
psycho_alloc_resource(device_t bus,device_t child,int type,int * rid,u_long start,u_long end,u_long count,u_int flags)1040 psycho_alloc_resource(device_t bus, device_t child, int type, int *rid,
1041 u_long start, u_long end, u_long count, u_int flags)
1042 {
1043 struct psycho_softc *sc;
1044
1045 if (type == SYS_RES_IRQ) {
1046 sc = device_get_softc(bus);
1047 start = end = INTMAP_VEC(sc->sc_ign, end);
1048 }
1049 return (ofw_pci_alloc_resource(bus, child, type, rid, start, end,
1050 count, flags));
1051 }
1052
1053 static void
psycho_setup_device(device_t bus,device_t child)1054 psycho_setup_device(device_t bus, device_t child)
1055 {
1056 struct psycho_softc *sc;
1057 uint32_t rev;
1058
1059 sc = device_get_softc(bus);
1060 /*
1061 * Revision 0 EBus bridges have a bug which prevents them from
1062 * working when bus parking is enabled.
1063 */
1064 if ((strcmp(ofw_bus_get_name(child), "ebus") == 0 ||
1065 strcmp(ofw_bus_get_name(child), "pci108e,1000") == 0) &&
1066 OF_getprop(ofw_bus_get_node(child), "revision-id", &rev,
1067 sizeof(rev)) > 0 && rev == 0)
1068 PCICTL_WRITE8(sc, PCR_CS, PCICTL_READ8(sc, PCR_CS) &
1069 ~PCICTL_ARB_PARK);
1070 }
1071