1 /*-
2 * Copyright (C) 2002 Benno Rice.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/module.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/kernel.h>
35
36 #include <dev/ofw/openfirm.h>
37 #include <dev/ofw/ofw_pci.h>
38 #include <dev/ofw/ofw_bus.h>
39 #include <dev/ofw/ofw_bus_subr.h>
40
41 #include <dev/pci/pcivar.h>
42 #include <dev/pci/pcireg.h>
43
44 #include <machine/bus.h>
45 #include <machine/intr_machdep.h>
46 #include <machine/md_var.h>
47 #include <machine/pio.h>
48 #include <machine/resource.h>
49
50 #include <sys/rman.h>
51
52 #include <powerpc/ofw/ofw_pci.h>
53 #include <powerpc/powermac/uninorthvar.h>
54
55 #include <vm/vm.h>
56 #include <vm/pmap.h>
57
58 #include "pcib_if.h"
59
60 #define UNINORTH_DEBUG 0
61
62 /*
63 * Device interface.
64 */
65 static int uninorth_probe(device_t);
66 static int uninorth_attach(device_t);
67
68 /*
69 * pcib interface.
70 */
71 static u_int32_t uninorth_read_config(device_t, u_int, u_int, u_int,
72 u_int, int);
73 static void uninorth_write_config(device_t, u_int, u_int, u_int,
74 u_int, u_int32_t, int);
75
76 /*
77 * Local routines.
78 */
79 static int uninorth_enable_config(struct uninorth_softc *, u_int,
80 u_int, u_int, u_int);
81
82 /*
83 * Driver methods.
84 */
85 static device_method_t uninorth_methods[] = {
86 /* Device interface */
87 DEVMETHOD(device_probe, uninorth_probe),
88 DEVMETHOD(device_attach, uninorth_attach),
89
90 /* pcib interface */
91 DEVMETHOD(pcib_read_config, uninorth_read_config),
92 DEVMETHOD(pcib_write_config, uninorth_write_config),
93
94 DEVMETHOD_END
95 };
96
97 static devclass_t uninorth_devclass;
98
99 DEFINE_CLASS_1(pcib, uninorth_driver, uninorth_methods,
100 sizeof(struct uninorth_softc), ofw_pci_driver);
101 DRIVER_MODULE(uninorth, ofwbus, uninorth_driver, uninorth_devclass, 0, 0);
102
103 static int
uninorth_probe(device_t dev)104 uninorth_probe(device_t dev)
105 {
106 const char *type, *compatible;
107
108 type = ofw_bus_get_type(dev);
109 compatible = ofw_bus_get_compat(dev);
110
111 if (type == NULL || compatible == NULL)
112 return (ENXIO);
113
114 if (strcmp(type, "pci") != 0)
115 return (ENXIO);
116
117 if (strcmp(compatible, "uni-north") == 0) {
118 device_set_desc(dev, "Apple UniNorth Host-PCI bridge");
119 return (0);
120 } else if (strcmp(compatible, "u3-agp") == 0) {
121 device_set_desc(dev, "Apple U3 Host-AGP bridge");
122 return (0);
123 } else if (strcmp(compatible, "u4-pcie") == 0) {
124 device_set_desc(dev, "IBM CPC945 PCI Express Root");
125 return (0);
126 }
127
128 return (ENXIO);
129 }
130
131 static int
uninorth_attach(device_t dev)132 uninorth_attach(device_t dev)
133 {
134 struct uninorth_softc *sc;
135 const char *compatible;
136 phandle_t node;
137 uint32_t reg[3];
138 uint64_t regbase;
139 cell_t acells;
140
141 node = ofw_bus_get_node(dev);
142 sc = device_get_softc(dev);
143
144 if (OF_getprop(node, "reg", reg, sizeof(reg)) < 8)
145 return (ENXIO);
146
147 sc->sc_ver = 0;
148 compatible = ofw_bus_get_compat(dev);
149 if (strcmp(compatible, "u3-agp") == 0)
150 sc->sc_ver = 3;
151 if (strcmp(compatible, "u4-pcie") == 0)
152 sc->sc_ver = 4;
153
154 acells = 1;
155 OF_getprop(OF_parent(node), "#address-cells", &acells, sizeof(acells));
156
157 regbase = reg[0];
158 if (acells == 2) {
159 regbase <<= 32;
160 regbase |= reg[1];
161 }
162
163 sc->sc_addr = (vm_offset_t)pmap_mapdev(regbase + 0x800000, PAGE_SIZE);
164 sc->sc_data = (vm_offset_t)pmap_mapdev(regbase + 0xc00000, PAGE_SIZE);
165
166 return (ofw_pci_attach(dev));
167 }
168
169 static u_int32_t
uninorth_read_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,int width)170 uninorth_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
171 int width)
172 {
173 struct uninorth_softc *sc;
174 vm_offset_t caoff;
175
176 sc = device_get_softc(dev);
177 caoff = sc->sc_data + (reg & 0x07);
178
179 if (uninorth_enable_config(sc, bus, slot, func, reg) != 0) {
180 switch (width) {
181 case 1:
182 return (in8rb(caoff));
183 break;
184 case 2:
185 return (in16rb(caoff));
186 break;
187 case 4:
188 return (in32rb(caoff));
189 break;
190 }
191 }
192
193 return (0xffffffff);
194 }
195
196 static void
uninorth_write_config(device_t dev,u_int bus,u_int slot,u_int func,u_int reg,u_int32_t val,int width)197 uninorth_write_config(device_t dev, u_int bus, u_int slot, u_int func,
198 u_int reg, u_int32_t val, int width)
199 {
200 struct uninorth_softc *sc;
201 vm_offset_t caoff;
202
203 sc = device_get_softc(dev);
204 caoff = sc->sc_data + (reg & 0x07);
205
206 if (uninorth_enable_config(sc, bus, slot, func, reg)) {
207 switch (width) {
208 case 1:
209 out8rb(caoff, val);
210 break;
211 case 2:
212 out16rb(caoff, val);
213 break;
214 case 4:
215 out32rb(caoff, val);
216 break;
217 }
218 }
219 }
220
221 static int
uninorth_enable_config(struct uninorth_softc * sc,u_int bus,u_int slot,u_int func,u_int reg)222 uninorth_enable_config(struct uninorth_softc *sc, u_int bus, u_int slot,
223 u_int func, u_int reg)
224 {
225 uint32_t cfgval;
226 uint32_t pass;
227
228 if (resource_int_value(device_get_name(sc->pci_sc.sc_dev),
229 device_get_unit(sc->pci_sc.sc_dev), "skipslot", &pass) == 0) {
230 if (pass == slot)
231 return (0);
232 }
233
234 /*
235 * Issue type 0 configuration space accesses for the root bus.
236 *
237 * NOTE: On U4, issue only type 1 accesses. There is a secret
238 * PCI Express <-> PCI Express bridge not present in the device tree,
239 * and we need to route all of our configuration space through it.
240 */
241 if (sc->pci_sc.sc_bus == bus && sc->sc_ver < 4) {
242 /*
243 * No slots less than 11 on the primary bus on U3 and lower
244 */
245 if (slot < 11)
246 return (0);
247
248 cfgval = (1 << slot) | (func << 8) | (reg & 0xfc);
249 } else {
250 cfgval = (bus << 16) | (slot << 11) | (func << 8) |
251 (reg & 0xfc) | 1;
252 }
253
254 /* Set extended register bits on U4 */
255 if (sc->sc_ver == 4)
256 cfgval |= (reg >> 8) << 28;
257
258 do {
259 out32rb(sc->sc_addr, cfgval);
260 } while (in32rb(sc->sc_addr) != cfgval);
261
262 return (1);
263 }
264
265