1 /*-
2 * Copyright(c) 2002-2011 Exar Corp.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification are permitted provided the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 *
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * 3. Neither the name of the Exar Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31 /*$FreeBSD$*/
32
33 #include <dev/vxge/vxgehal/vxgehal.h>
34
35 /*
36 * __hal_srpcim_alarm_process - Process Alarms.
37 * @hldev: HAL Device
38 * @srpcim_id: srpcim index
39 * @skip_alarms: Flag to indicate if not to clear the alarms
40 *
41 * Process srpcim alarms.
42 *
43 */
44 vxge_hal_status_e
__hal_srpcim_alarm_process(__hal_device_t * hldev,u32 srpcim_id,u32 skip_alarms)45 __hal_srpcim_alarm_process(
46 __hal_device_t * hldev,
47 u32 srpcim_id,
48 u32 skip_alarms)
49 {
50 u64 val64;
51 u64 alarm_status;
52 u64 pic_status;
53 u64 xgmac_status;
54 vxge_hal_srpcim_reg_t *srpcim_reg;
55
56 vxge_assert(hldev != NULL);
57
58 vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
59 __FILE__, __func__, __LINE__);
60
61 vxge_hal_trace_log_srpcim_irq("hldev = 0x"VXGE_OS_STXFMT,
62 (ptr_t) hldev);
63
64 srpcim_reg = hldev->srpcim_reg[srpcim_id];
65
66 alarm_status = vxge_os_pio_mem_read64(hldev->header.pdev,
67 hldev->header.regh0,
68 &srpcim_reg->srpcim_general_int_status);
69
70 vxge_hal_info_log_srpcim_irq("alarm_status = 0x"VXGE_OS_STXFMT,
71 (ptr_t) alarm_status);
72
73 if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT) {
74
75 xgmac_status = vxge_os_pio_mem_read64(hldev->header.pdev,
76 hldev->header.regh0,
77 &srpcim_reg->xgmac_sr_int_status);
78
79 vxge_hal_info_log_srpcim_irq("xgmac_status = 0x"VXGE_OS_STXFMT,
80 (ptr_t) xgmac_status);
81
82 if (xgmac_status &
83 VXGE_HAL_XGMAC_SR_INT_STATUS_ASIC_NTWK_SR_ERR_INT) {
84
85 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
86 hldev->header.regh0,
87 &srpcim_reg->asic_ntwk_sr_err_reg);
88
89 vxge_hal_info_log_srpcim_irq("asic_ntwk_sr_err_reg = \
90 0x"VXGE_OS_STXFMT, (ptr_t) val64);
91
92 if (!skip_alarms)
93 vxge_os_pio_mem_write64(hldev->header.pdev,
94 hldev->header.regh0,
95 VXGE_HAL_INTR_MASK_ALL,
96 &srpcim_reg->asic_ntwk_sr_err_reg);
97
98 }
99 }
100
101 if (alarm_status & VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT) {
102
103 pic_status = vxge_os_pio_mem_read64(hldev->header.pdev,
104 hldev->header.regh0,
105 &srpcim_reg->srpcim_ppif_int_status);
106
107 vxge_hal_info_log_srpcim_irq("pic_status = 0x"VXGE_OS_STXFMT,
108 (ptr_t) pic_status);
109
110 if (pic_status &
111 VXGE_HAL_SRPCIM_PPIF_INT_STATUS_SRPCIM_GEN_ERRORS_INT) {
112
113 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
114 hldev->header.regh0,
115 &srpcim_reg->srpcim_gen_errors_reg);
116
117 vxge_hal_info_log_srpcim_irq("srpcim_gen_errors_reg = \
118 0x"VXGE_OS_STXFMT, (ptr_t) val64);
119
120 if (!skip_alarms)
121 vxge_os_pio_mem_write64(hldev->header.pdev,
122 hldev->header.regh0,
123 VXGE_HAL_INTR_MASK_ALL,
124 &srpcim_reg->srpcim_gen_errors_reg);
125 }
126
127 if (pic_status &
128 VXGE_HAL_SRPCIM_PPIF_INT_STATUS_MRPCIM_TO_SRPCIM_ALARM) {
129
130 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
131 hldev->header.regh0,
132 &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
133
134 vxge_hal_info_log_srpcim_irq("mrpcim_to_srpcim_alarm_reg = \
135 0x"VXGE_OS_STXFMT, (ptr_t) val64);
136
137 if (!skip_alarms)
138 vxge_os_pio_mem_write64(hldev->header.pdev,
139 hldev->header.regh0,
140 VXGE_HAL_INTR_MASK_ALL,
141 &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
142
143 }
144 }
145
146 if (alarm_status & ~(
147 VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_PIC_INT |
148 VXGE_HAL_SRPCIM_GENERAL_INT_STATUS_XMAC_INT)) {
149 vxge_hal_trace_log_srpcim_irq("%s:%s:%d Unknown Alarm",
150 __FILE__, __func__, __LINE__);
151 }
152
153 vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = 0",
154 __FILE__, __func__, __LINE__);
155
156 return (VXGE_HAL_OK);
157 }
158
159 /*
160 * vxge_hal_srpcim_alarm_process - Process srpcim Alarms.
161 * @devh: Device Handle.
162 * @skip_alarms: Flag to indicate if not to clear the alarms
163 *
164 * Process srpcim alarms.
165 *
166 */
167 vxge_hal_status_e
vxge_hal_srpcim_alarm_process(vxge_hal_device_h devh,u32 skip_alarms)168 vxge_hal_srpcim_alarm_process(
169 vxge_hal_device_h devh,
170 u32 skip_alarms)
171 {
172 u32 i;
173 u64 val64;
174 vxge_hal_status_e status = VXGE_HAL_OK;
175 __hal_device_t *hldev = (__hal_device_t *) devh;
176
177 vxge_assert(devh != NULL);
178
179 vxge_hal_trace_log_srpcim_irq("==> %s:%s:%d",
180 __FILE__, __func__, __LINE__);
181
182 vxge_hal_trace_log_srpcim_irq("devh = 0x"VXGE_OS_STXFMT,
183 (ptr_t) devh);
184
185 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
186 vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
187 __FILE__, __func__, __LINE__,
188 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
189
190 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
191
192 }
193
194 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
195
196 val64 = vxge_os_pio_mem_read64(hldev->header.pdev,
197 hldev->header.regh0,
198 &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
199
200 vxge_hal_trace_log_srpcim_irq("srpcim_to_mrpcim_alarm_reg = \
201 0x"VXGE_OS_STXFMT, (ptr_t) val64);
202
203 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
204
205 if (val64 & mBIT(i)) {
206 status = __hal_srpcim_alarm_process(hldev,
207 i, skip_alarms);
208 }
209 }
210
211 if (!skip_alarms)
212 vxge_os_pio_mem_write64(hldev->header.pdev,
213 hldev->header.regh0,
214 VXGE_HAL_INTR_MASK_ALL,
215 &hldev->mrpcim_reg->srpcim_to_mrpcim_alarm_reg);
216 } else {
217 status = __hal_srpcim_alarm_process(hldev,
218 hldev->srpcim_id, skip_alarms);
219 }
220
221 vxge_hal_trace_log_srpcim_irq("<== %s:%s:%d Result = %d",
222 __FILE__, __func__, __LINE__, status);
223
224 return (status);
225 }
226
227 /*
228 * __hal_srpcim_intr_enable - Enable srpcim interrupts.
229 * @hldev: Hal Device.
230 * @srpcim_id: SRPCIM Id
231 *
232 * Enable srpcim interrupts.
233 *
234 * See also: __hal_srpcim_intr_disable()
235 */
236 vxge_hal_status_e
__hal_srpcim_intr_enable(__hal_device_t * hldev,u32 srpcim_id)237 __hal_srpcim_intr_enable(
238 __hal_device_t * hldev,
239 u32 srpcim_id)
240 {
241 vxge_hal_srpcim_reg_t *srpcim_reg;
242
243 vxge_assert(hldev != NULL);
244
245 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
246 __FILE__, __func__, __LINE__);
247
248 vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
249 (ptr_t) hldev);
250
251 srpcim_reg = hldev->srpcim_reg[srpcim_id];
252
253 vxge_os_pio_mem_write64(hldev->header.pdev,
254 hldev->header.regh0,
255 VXGE_HAL_INTR_MASK_ALL,
256 &srpcim_reg->srpcim_gen_errors_reg);
257
258 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
259 hldev->header.regh0,
260 (u32) VXGE_HAL_INTR_MASK_ALL,
261 &srpcim_reg->mrpcim_to_srpcim_alarm_reg);
262
263 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
264 hldev->header.regh0,
265 (u32) VXGE_HAL_INTR_MASK_ALL,
266 &srpcim_reg->vpath_to_srpcim_alarm_reg);
267
268 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
269 hldev->header.regh0,
270 (u32) VXGE_HAL_INTR_MASK_ALL,
271 &srpcim_reg->srpcim_ppif_int_status);
272
273 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
274 hldev->header.regh0,
275 (u32) VXGE_HAL_INTR_MASK_ALL,
276 &srpcim_reg->mrpcim_msg_reg);
277
278 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
279 hldev->header.regh0,
280 (u32) VXGE_HAL_INTR_MASK_ALL,
281 &srpcim_reg->vpath_msg_reg);
282
283 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
284 hldev->header.regh0,
285 (u32) VXGE_HAL_INTR_MASK_ALL,
286 &srpcim_reg->srpcim_pcipif_int_status);
287
288 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
289 hldev->header.regh0,
290 (u32) VXGE_HAL_INTR_MASK_ALL,
291 &srpcim_reg->asic_ntwk_sr_err_reg);
292
293 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
294 hldev->header.regh0,
295 (u32) VXGE_HAL_INTR_MASK_ALL,
296 &srpcim_reg->xgmac_sr_int_status);
297
298 vxge_os_pio_mem_read64(hldev->header.pdev,
299 hldev->header.regh0,
300 &srpcim_reg->srpcim_general_int_status);
301
302 /* Unmask the individual interrupts. */
303 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
304 hldev->header.regh0,
305 0,
306 &srpcim_reg->vpath_msg_mask);
307
308 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
309 hldev->header.regh0,
310 0,
311 &srpcim_reg->srpcim_pcipif_int_mask);
312
313 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
314 hldev->header.regh0,
315 (u32) bVAL32(~VXGE_HAL_SRPCIM_GENERAL_INT_MASK_PCI_INT, 0),
316 &srpcim_reg->srpcim_general_int_mask);
317
318 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
319 __FILE__, __func__, __LINE__);
320
321 return (VXGE_HAL_OK);
322 }
323
324 /*
325 * vxge_hal_srpcim_intr_enable - Enable srpcim interrupts.
326 * @devh: Hal Device.
327 *
328 * Enable srpcim interrupts.
329 *
330 * See also: vxge_hal_srpcim_intr_disable()
331 */
332 vxge_hal_status_e
vxge_hal_srpcim_intr_enable(vxge_hal_device_h devh)333 vxge_hal_srpcim_intr_enable(
334 vxge_hal_device_h devh)
335 {
336 u32 i;
337 vxge_hal_status_e status;
338 __hal_device_t *hldev = (__hal_device_t *) devh;
339
340 vxge_assert(devh != NULL);
341
342 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
343 __FILE__, __func__, __LINE__);
344
345 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
346 (ptr_t) devh);
347
348 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
349 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
350 __FILE__, __func__, __LINE__,
351 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
352
353 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
354
355 }
356
357 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
358
359 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
360
361 status = __hal_srpcim_intr_enable(hldev, i);
362
363 }
364
365 } else {
366 status = __hal_srpcim_intr_enable(hldev, hldev->srpcim_id);
367 }
368
369 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
370 __FILE__, __func__, __LINE__, status);
371
372 return (status);
373 }
374
375 /*
376 * __hal_srpcim_intr_disable - Disable srpcim interrupts.
377 * @hldev: Hal Device.
378 * @srpcim_id: SRPCIM Id
379 *
380 * Disable srpcim interrupts.
381 *
382 * See also: __hal_srpcim_intr_enable()
383 */
384 vxge_hal_status_e
__hal_srpcim_intr_disable(__hal_device_t * hldev,u32 srpcim_id)385 __hal_srpcim_intr_disable(
386 __hal_device_t * hldev,
387 u32 srpcim_id)
388 {
389 vxge_hal_srpcim_reg_t *srpcim_reg;
390
391 vxge_assert(hldev != NULL);
392
393 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
394 __FILE__, __func__, __LINE__);
395
396 vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
397 (ptr_t) hldev);
398
399 srpcim_reg = hldev->srpcim_reg[srpcim_id];
400
401 /* Mask the individual interrupts. */
402 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
403 hldev->header.regh0,
404 (u32) VXGE_HAL_INTR_MASK_ALL,
405 &srpcim_reg->vpath_msg_mask);
406
407 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
408 hldev->header.regh0,
409 (u32) VXGE_HAL_INTR_MASK_ALL,
410 &srpcim_reg->srpcim_pcipif_int_mask);
411
412 vxge_hal_pio_mem_write32_upper(
413 hldev->header.pdev,
414 hldev->header.regh0,
415 (u32) VXGE_HAL_INTR_MASK_ALL,
416 &srpcim_reg->srpcim_general_int_mask);
417
418 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
419 __FILE__, __func__, __LINE__);
420
421 return (VXGE_HAL_OK);
422
423 }
424
425 /*
426 * vxge_hal_srpcim_intr_disable - Disable srpcim interrupts.
427 * @devh: Hal Device.
428 *
429 * Disable srpcim interrupts.
430 *
431 * See also: vxge_hal_srpcim_intr_enable()
432 */
433 vxge_hal_status_e
vxge_hal_srpcim_intr_disable(vxge_hal_device_h devh)434 vxge_hal_srpcim_intr_disable(
435 vxge_hal_device_h devh)
436 {
437 u32 i;
438 vxge_hal_status_e status;
439 __hal_device_t *hldev = (__hal_device_t *) devh;
440
441 vxge_assert(devh != NULL);
442
443 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
444 __FILE__, __func__, __LINE__);
445
446 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
447 (ptr_t) devh);
448
449 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
450 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
451 __FILE__, __func__, __LINE__,
452 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
453
454 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
455
456 }
457
458 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
459
460 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
461
462 status = __hal_srpcim_intr_disable(hldev, i);
463
464 }
465
466 } else {
467 status = __hal_srpcim_intr_disable(hldev, hldev->srpcim_id);
468 }
469
470 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
471 __FILE__, __func__, __LINE__, status);
472
473 return (status);
474 }
475
476 /*
477 * vxge_hal_srpcim_msix_set - Associate MSIX vector with srpcim alarm
478 * @hldev: HAL device.
479 * @alarm_msix_id: MSIX vector for alarm.
480 *
481 * This API will associate a given MSIX vector numbers with srpcim alarm
482 */
483 vxge_hal_status_e
vxge_hal_srpcim_msix_set(vxge_hal_device_h devh,int alarm_msix_id)484 vxge_hal_srpcim_msix_set(vxge_hal_device_h devh, int alarm_msix_id)
485 {
486 u32 i;
487 vxge_hal_status_e status = VXGE_HAL_OK;
488 __hal_device_t *hldev = (__hal_device_t *) devh;
489
490 vxge_assert(devh != NULL);
491
492 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
493 __FILE__, __func__, __LINE__);
494
495 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
496 (ptr_t) devh);
497
498 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
499 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
500 __FILE__, __func__, __LINE__,
501 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
502
503 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
504
505 }
506
507 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
508
509 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
510
511 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
512 hldev->header.regh0,
513 (u32) bVAL32(
514 VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
515 alarm_msix_id),
516 0),
517 &hldev->srpcim_reg[i]->srpcim_interrupt_cfg1);
518
519 }
520
521 } else {
522 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
523 hldev->header.regh0,
524 (u32) bVAL32(
525 VXGE_HAL_SRPCIM_INTERRUPT_CFG1_ALARM_MAP_TO_MSG(
526 alarm_msix_id),
527 0),
528 &hldev->srpcim_reg[hldev->srpcim_id]->
529 srpcim_interrupt_cfg1);
530 }
531
532 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
533 __FILE__, __func__, __LINE__, status);
534
535 return (status);
536 }
537
538 /*
539 * vxge_hal_srpcim_msix_mask - Mask MSIX Vector.
540 * @hldev: HAL device.
541 *
542 * The function masks the srpcim msix interrupt
543 *
544 */
545 void
vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh)546 vxge_hal_srpcim_msix_mask(vxge_hal_device_h devh)
547 {
548 u32 i;
549 __hal_device_t *hldev = (__hal_device_t *) devh;
550
551 vxge_assert(devh != NULL);
552
553 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
554 __FILE__, __func__, __LINE__);
555
556 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
557 (ptr_t) devh);
558
559 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
560 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
561 __FILE__, __func__, __LINE__,
562 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
563
564 return;
565
566 }
567
568 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
569
570 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
571
572 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
573 hldev->header.regh0,
574 (u32) bVAL32(
575 VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
576 0),
577 &hldev->srpcim_reg[i]->srpcim_set_msix_mask);
578
579 }
580
581 } else {
582 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
583 hldev->header.regh0,
584 (u32) bVAL32(
585 VXGE_HAL_SRPCIM_SET_MSIX_MASK_SRPCIM_SET_MSIX_MASK,
586 0),
587 &hldev->srpcim_reg[hldev->srpcim_id]->srpcim_set_msix_mask);
588 }
589
590 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
591 __FILE__, __func__, __LINE__);
592 }
593
594 /*
595 * vxge_hal_srpcim_msix_clear - Clear MSIX Vector.
596 * @hldev: HAL device.
597 *
598 * The function clears the srpcim msix interrupt
599 *
600 */
601 void
vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh)602 vxge_hal_srpcim_msix_clear(vxge_hal_device_h devh)
603 {
604 u32 i;
605 __hal_device_t *hldev = (__hal_device_t *) devh;
606
607 vxge_assert(devh != NULL);
608
609 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
610 __FILE__, __func__, __LINE__);
611
612 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
613 (ptr_t) devh);
614
615 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
616 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
617 __FILE__, __func__, __LINE__,
618 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
619
620 return;
621
622 }
623
624 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
625
626 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
627
628 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
629 hldev->header.regh0,
630 (u32) bVAL32(
631 VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
632 0),
633 &hldev->srpcim_reg[i]->srpcim_clear_msix_mask);
634
635 }
636
637 } else {
638 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
639 hldev->header.regh0,
640 (u32) bVAL32(
641 VXGE_HAL_SRPCIM_CLEAR_MSIX_MASK_SRPCIM_CLEAR_MSIX_MASK,
642 0),
643 &hldev->srpcim_reg[hldev->srpcim_id]->
644 srpcim_clear_msix_mask);
645 }
646
647 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
648 __FILE__, __func__, __LINE__);
649 }
650
651 /*
652 * vxge_hal_srpcim_msix_unmask - Unmask MSIX Vector.
653 * @hldev: HAL device.
654 *
655 * The function unmasks the srpcim msix interrupt
656 *
657 */
658 void
vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh)659 vxge_hal_srpcim_msix_unmask(vxge_hal_device_h devh)
660 {
661 u32 i;
662 __hal_device_t *hldev = (__hal_device_t *) devh;
663
664 vxge_assert(devh != NULL);
665
666 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
667 __FILE__, __func__, __LINE__);
668
669 vxge_hal_trace_log_srpcim("devh = 0x"VXGE_OS_STXFMT,
670 (ptr_t) devh);
671
672 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
673 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
674 __FILE__, __func__, __LINE__,
675 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
676
677 return;
678
679 }
680
681 if (hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM) {
682
683 for (i = 0; i < VXGE_HAL_TITAN_SRPCIM_REG_SPACES; i++) {
684
685 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
686 hldev->header.regh0,
687 (u32) bVAL32(
688 VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
689 0),
690 &hldev->srpcim_reg[i]->srpcim_clr_msix_one_shot);
691
692 }
693
694 } else {
695 vxge_hal_pio_mem_write32_upper(hldev->header.pdev,
696 hldev->header.regh0,
697 (u32) bVAL32(
698 VXGE_HAL_SRPCIM_CLR_MSIX_ONE_SHOT_SRPCIM_CLR_MSIX_ONE_SHOT,
699 0),
700 &hldev->srpcim_reg[hldev->srpcim_id]->
701 srpcim_clr_msix_one_shot);
702 }
703
704 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
705 __FILE__, __func__, __LINE__);
706 }
707
708 /*
709 * __hal_srpcim_initialize - Initialize srpcim.
710 * @hldev: HAL Device
711 *
712 * Initialize srpcim.
713 *
714 */
715 vxge_hal_status_e
__hal_srpcim_initialize(__hal_device_t * hldev)716 __hal_srpcim_initialize(
717 __hal_device_t * hldev)
718 {
719 vxge_assert(hldev != NULL);
720
721 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
722 __FILE__, __func__, __LINE__);
723
724 vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
725 (ptr_t) hldev);
726
727 if (!(hldev->access_rights & VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM)) {
728 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
729 __FILE__, __func__, __LINE__,
730 VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
731 return (VXGE_HAL_ERR_PRIVILAGED_OPEARATION);
732 }
733
734 hldev->srpcim = (__hal_srpcim_t *)
735 vxge_os_malloc(hldev->header.pdev, sizeof(__hal_srpcim_t));
736
737 if (hldev->srpcim == NULL) {
738 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
739 __FILE__, __func__, __LINE__, VXGE_HAL_ERR_OUT_OF_MEMORY);
740 return (VXGE_HAL_ERR_OUT_OF_MEMORY);
741 }
742
743 vxge_os_memzero(hldev->srpcim, sizeof(__hal_srpcim_t));
744
745 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
746 __FILE__, __func__, __LINE__);
747
748 return (VXGE_HAL_OK);
749 }
750
751 /*
752 * __hal_srpcim_terminate - Terminate srpcim.
753 * @hldev: HAL Device
754 *
755 * Terminate srpcim.
756 *
757 */
758 vxge_hal_status_e
__hal_srpcim_terminate(__hal_device_t * hldev)759 __hal_srpcim_terminate(
760 __hal_device_t * hldev)
761 {
762 vxge_hal_status_e status = VXGE_HAL_OK;
763
764 vxge_assert(hldev != NULL);
765
766 vxge_hal_trace_log_srpcim("==> %s:%s:%d",
767 __FILE__, __func__, __LINE__);
768
769 vxge_hal_trace_log_srpcim("hldev = 0x"VXGE_OS_STXFMT,
770 (ptr_t) hldev);
771
772 if (hldev->srpcim == NULL) {
773 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = %d",
774 __FILE__, __func__, __LINE__, status);
775 return (status);
776 }
777
778 vxge_os_free(hldev->header.pdev,
779 hldev->srpcim, sizeof(__hal_srpcim_t));
780
781 hldev->srpcim = NULL;
782
783 vxge_hal_trace_log_srpcim("<== %s:%s:%d Result = 0",
784 __FILE__, __func__, __LINE__);
785
786 return (VXGE_HAL_OK);
787 }
788