1 /* $FreeBSD$ */ 2 /* $NecBSD: dp83932reg.h,v 1.2 1999/02/12 05:50:13 kmatsuda Exp $ */ 3 /* $NetBSD: if_snreg.h,v 1.4 1997/06/15 20:20:12 scottr Exp $ */ 4 5 /*- 6 * Copyright (c) 1991 Algorithmics Ltd (http://www.algor.co.uk) 7 * You may use, copy, and modify this program so long as you retain the 8 * copyright line. 9 */ 10 11 /* 12 * if_snreg.h -- National Semiconductor DP8393X (SONIC) register defs 13 */ 14 15 /* 16 * SONIC registers as seen by the processor 17 */ 18 #define SNCR_CR 0x00 /* Command */ 19 #define SNCR_DCR 0x01 /* Data Configuration */ 20 #define SNCR_RCR 0x02 /* Receive Control */ 21 #define SNCR_TCR 0x03 /* Transmit Control */ 22 #define SNCR_IMR 0x04 /* Interrupt Mask */ 23 #define SNCR_ISR 0x05 /* Interrupt Status */ 24 #define SNCR_UTDA 0x06 /* Upper Transmit Descriptor Address */ 25 #define SNCR_CTDA 0x07 /* Current Transmit Descriptor Address */ 26 #define SNCR_TPS 0x08 /* Transmit Packet Size */ 27 #define SNCR_TFC 0x09 /* Transmit Fragment Count */ 28 #define SNCR_TSA0 0x0a /* Transmit Start Address 0 */ 29 #define SNCR_TSA1 0x0b /* Transmit Start Address 1 */ 30 #define SNCR_TFS 0x0c /* Transmit Fragment Size */ 31 #define SNCR_URDA 0x0d /* Upper Receive Descriptor Address */ 32 #define SNCR_CRDA 0x0e /* Current Receive Descriptor Address */ 33 #define SNCR_CRBA0 0x0f /* Current Receive Buffer Address 0 */ 34 #define SNCR_CRBA1 0x10 /* Current Receive Buffer Address 1 */ 35 #define SNCR_RBWC0 0x11 /* Remaining Buffer Word Count 0 */ 36 #define SNCR_RBWC1 0x12 /* Remaining Buffer Word Count 1 */ 37 #define SNCR_EOBC 0x13 /* End Of Buffer Word Count */ 38 #define SNCR_URRA 0x14 /* Upper Receive Resource Address */ 39 #define SNCR_RSA 0x15 /* Resource Start Address */ 40 #define SNCR_REA 0x16 /* Resource End Address */ 41 #define SNCR_RRP 0x17 /* Resource Read Pointer */ 42 #define SNCR_RWP 0x18 /* Resource Write Pointer */ 43 #define SNCR_TRBA0 0x19 /* Temporary Receive Buffer Address 0 */ 44 #define SNCR_TRBA1 0x1a /* Temporary Receive Buffer Address 1 */ 45 #define SNCR_TBWC0 0x1b /* Temporary Buffer Word Count 0 */ 46 #define SNCR_TBWC1 0x1c /* Temporary Buffer Word Count 1 */ 47 #define SNCR_ADDR0 0x1d /* Address Generator 0 */ 48 #define SNCR_ADDR1 0x1e /* Address Generator 1 */ 49 #define SNCR_LLFA 0x1f /* Last Link Field Address */ 50 #define SNCR_TTDA 0x20 /* Temp Transmit Descriptor Address */ 51 #define SNCR_CEP 0x21 /* CAM Entry Pointer */ 52 #define SNCR_CAP2 0x22 /* CAM Address Port 2 */ 53 #define SNCR_CAP1 0x23 /* CAM Address Port 1 */ 54 #define SNCR_CAP0 0x24 /* CAM Address Port 0 */ 55 #define SNCR_CE 0x25 /* CAM Enable */ 56 #define SNCR_CDP 0x26 /* CAM Descriptor Pointer */ 57 #define SNCR_CDC 0x27 /* CAM Descriptor Count */ 58 #define SNCR_SR 0x28 /* Silicon Revision */ 59 #define SNCR_WT0 0x29 /* Watchdog Timer 0 */ 60 #define SNCR_WT1 0x2a /* Watchdog Timer 1 */ 61 #define SNCR_RSC 0x2b /* Receive Sequence Counter */ 62 #define SNCR_CRCT 0x2c /* CRC Error Tally */ 63 #define SNCR_FAET 0x2d /* FAE Tally */ 64 #define SNCR_MPT 0x2e /* Missed Packet Tally */ 65 #define SNCR_MDT 0x2f /* Maximum Deferral Timer */ 66 #define SNCR_RTC 0x30 /* Receive Test Control */ 67 #define SNCR_TTC 0x31 /* Transmit Test Control */ 68 #define SNCR_DTC 0x32 /* DMA Test Control */ 69 #define SNCR_CC0 0x33 /* CAM Comparison 0 */ 70 #define SNCR_CC1 0x34 /* CAM Comparison 1 */ 71 #define SNCR_CC2 0x35 /* CAM Comparison 2 */ 72 #define SNCR_CM 0x36 /* CAM Match */ 73 #define SNCR_RES1 0x37 /* reserved */ 74 #define SNCR_RES2 0x38 /* reserved */ 75 #define SNCR_RBC 0x39 /* Receiver Byte Count */ 76 #define SNCR_RES3 0x3a /* reserved */ 77 #define SNCR_TBO 0x3b /* Transmitter Backoff Counter */ 78 #define SNCR_TRC 0x3c /* Transmitter Random Counter */ 79 #define SNCR_TBM 0x3d /* Transmitter Backoff Mask */ 80 #define SNCR_RES4 0x3e /* Reserved */ 81 #define SNCR_DCR2 0x3f /* Data Configuration 2 (AVF) */ 82 83 #define SNC_NREGS 0x40 84 85 /* 86 * Register Interpretations 87 */ 88 89 /* 90 * The command register is used for issuing commands to the SONIC. 91 * With the exception of CR_RST, the bit is reset when the operation 92 * completes. 93 */ 94 #define CR_LCAM 0x0200 /* load CAM with descriptor at s_cdp */ 95 #define CR_RRRA 0x0100 /* read next RRA descriptor at s_rrp */ 96 #define CR_RST 0x0080 /* software reset */ 97 #define CR_ST 0x0020 /* start timer */ 98 #define CR_STP 0x0010 /* stop timer */ 99 #define CR_RXEN 0x0008 /* receiver enable */ 100 #define CR_RXDIS 0x0004 /* receiver disable */ 101 #define CR_TXP 0x0002 /* transmit packets */ 102 #define CR_HTX 0x0001 /* halt transmission */ 103 104 /* 105 * The data configuration register establishes the SONIC's bus cycle 106 * operation. This register can only be accessed when the SONIC is in 107 * reset mode (s_cr.CR_RST is set.) 108 */ 109 #define DCR_EXBUS 0x8000 /* extended bus mode (AVF) */ 110 #define DCR_LBR 0x2000 /* latched bus retry */ 111 #define DCR_PO1 0x1000 /* programmable output 1 */ 112 #define DCR_PO0 0x0800 /* programmable output 0 */ 113 #define DCR_STERM 0x0400 /* synchronous termination */ 114 #define DCR_USR1 0x0200 /* reflects USR1 input pin */ 115 #define DCR_USR0 0x0100 /* reflects USR0 input pin */ 116 #define DCR_WC1 0x0080 /* wait state control 1 */ 117 #define DCR_WC0 0x0040 /* wait state control 0 */ 118 #define DCR_DW 0x0020 /* data width select */ 119 #define DCR_BMS 0x0010 /* DMA block mode select */ 120 #define DCR_RFT1 0x0008 /* receive FIFO threshold control 1 */ 121 #define DCR_RFT0 0x0004 /* receive FIFO threshold control 0 */ 122 #define DCR_TFT1 0x0002 /* transmit FIFO threshold control 1 */ 123 #define DCR_TFT0 0x0001 /* transmit FIFO threshold control 0 */ 124 125 /* data configuration register aliases */ 126 #define DCR_SYNC DCR_STERM /* synchronous (memory cycle 2 clocks) */ 127 #define DCR_ASYNC 0 /* asynchronous (memory cycle 3 clocks) */ 128 129 #define DCR_WAIT0 0 /* 0 wait states added */ 130 #define DCR_WAIT1 DCR_WC0 /* 1 wait state added */ 131 #define DCR_WAIT2 DCR_WC1 /* 2 wait states added */ 132 #define DCR_WAIT3 (DCR_WC1|DCR_WC0) /* 3 wait states added */ 133 134 #define DCR_DW16 0 /* use 16-bit DMA accesses */ 135 #define DCR_DW32 DCR_DW /* use 32-bit DMA accesses */ 136 137 #define DCR_DMAEF 0 /* DMA until TX/RX FIFO has emptied/filled */ 138 #define DCR_DMABLOCK DCR_BMS /* DMA until RX/TX threshold crossed */ 139 140 #define DCR_RFT4 0 /* receive threshold 4 bytes */ 141 #define DCR_RFT8 DCR_RFT0 /* receive threshold 8 bytes */ 142 #define DCR_RFT16 DCR_RFT1 /* receive threshold 16 bytes */ 143 #define DCR_RFT24 (DCR_RFT1|DCR_RFT0) /* receive threshold 24 bytes */ 144 145 #define DCR_TFT8 0 /* transmit threshold 8 bytes */ 146 #define DCR_TFT16 DCR_TFT0 /* transmit threshold 16 bytes */ 147 #define DCR_TFT24 DCR_TFT1 /* transmit threshold 24 bytes */ 148 #define DCR_TFT28 (DCR_TFT1|DCR_TFT0) /* transmit threshold 28 bytes */ 149 150 /* 151 * The receive control register is used to filter incoming packets and 152 * provides status information on packets received. 153 * The contents of the register are copied into the RXpkt.status field 154 * when a packet is received. RCR_MC - RCR_PRX are then reset. 155 */ 156 #define RCR_ERR 0x8000 /* accept packets with CRC errors */ 157 #define RCR_RNT 0x4000 /* accept runt (length < 64) packets */ 158 #define RCR_BRD 0x2000 /* accept broadcast packets */ 159 #define RCR_PRO 0x1000 /* accept all physical address packets */ 160 #define RCR_AMC 0x0800 /* accept all multicast packets */ 161 #define RCR_LB1 0x0400 /* loopback control 1 */ 162 #define RCR_LB0 0x0200 /* loopback control 0 */ 163 #define RCR_MC 0x0100 /* multicast packet received */ 164 #define RCR_BC 0x0080 /* broadcast packet received */ 165 #define RCR_LPKT 0x0040 /* last packet in RBA (RBWC < EOBC) */ 166 #define RCR_CRS 0x0020 /* carrier sense activity */ 167 #define RCR_COL 0x0010 /* collision activity */ 168 #define RCR_CRC 0x0008 /* CRC error */ 169 #define RCR_FAE 0x0004 /* frame alignment error */ 170 #define RCR_LBK 0x0002 /* loopback packet received */ 171 #define RCR_PRX 0x0001 /* packet received without errors */ 172 173 /* receiver control register aliases */ 174 /* the loopback control bits provide the following options */ 175 #define RCR_LBNONE 0 /* no loopback - normal operation */ 176 #define RCR_LBMAC RCR_LB0 /* MAC loopback */ 177 #define RCR_LBENDEC RCR_LB1 /* ENDEC loopback */ 178 #define RCR_LBTRANS (RCR_LB1|RCR_LB0) /* transceiver loopback */ 179 180 /* 181 * The transmit control register controls the SONIC's transmit operations. 182 * TCR_PINT - TCR_EXDIS are loaded from the TXpkt.config field at the 183 * start of transmission. TCR_EXD-TCR_PTX are cleared at the beginning 184 * of transmission and updated when the transmission is completed. 185 */ 186 #define TCR_PINT 0x8000 /* interrupt when transmission starts */ 187 #define TCR_POWC 0x4000 /* program out of window collision timer */ 188 #define TCR_CRCI 0x2000 /* transmit packet without 4 byte FCS */ 189 #define TCR_EXDIS 0x1000 /* disable excessive deferral timer */ 190 #define TCR_EXD 0x0400 /* excessive deferrals occurred (>3.2ms) */ 191 #define TCR_DEF 0x0200 /* deferred transmissions occurred */ 192 #define TCR_NCRS 0x0100 /* carrier not present during transmission */ 193 #define TCR_CRSL 0x0080 /* carrier lost during transmission */ 194 #define TCR_EXC 0x0040 /* excessive collisions (>16) detected */ 195 #define TCR_OWC 0x0020 /* out of window (bad) collision occurred */ 196 #define TCR_PMB 0x0008 /* packet monitored bad - the tansmitted 197 * packet had a bad source address or CRC */ 198 #define TCR_FU 0x0004 /* FIFO underrun (memory access failed) */ 199 #define TCR_BCM 0x0002 /* byte count mismatch (TXpkt.pkt_size 200 * != sum(TXpkt.frag_size) */ 201 #define TCR_PTX 0x0001 /* packet transmitted without errors */ 202 #define TCR_NC 0xf000 /* after transmission, # of colls */ 203 204 /* transmit control register aliases */ 205 #define TCR_OWCSFD 0 /* start after start of frame delimiter */ 206 #define TCR_OWCPRE TCR_POWC /* start after first bit of preamble */ 207 208 209 /* 210 * The interrupt mask register masks the interrupts that 211 * are generated from the interrupt status register. 212 * All reserved bits should be written with 0. 213 */ 214 #define IMR_BREN 0x4000 /* bus retry occurred enable */ 215 #define IMR_HBLEN 0x2000 /* heartbeat lost enable */ 216 #define IMR_LCDEN 0x1000 /* load CAM done interrupt enable */ 217 #define IMR_PINTEN 0x0800 /* programmable interrupt enable */ 218 #define IMR_PRXEN 0x0400 /* packet received enable */ 219 #define IMR_PTXEN 0x0200 /* packet transmitted enable */ 220 #define IMR_TXEREN 0x0100 /* transmit error enable */ 221 #define IMR_TCEN 0x0080 /* timer complete enable */ 222 #define IMR_RDEEN 0x0040 /* receive descriptors exhausted enable */ 223 #define IMR_RBEEN 0x0020 /* receive buffers exhausted enable */ 224 #define IMR_RBAEEN 0x0010 /* receive buffer area exceeded enable */ 225 #define IMR_CRCEN 0x0008 /* CRC tally counter rollover enable */ 226 #define IMR_FAEEN 0x0004 /* FAE tally counter rollover enable */ 227 #define IMR_MPEN 0x0002 /* MP tally counter rollover enable */ 228 #define IMR_RFOEN 0x0001 /* receive FIFO overrun enable */ 229 230 231 /* 232 * The interrupt status register indicates the source of an interrupt when 233 * the INT pin goes active. The interrupt is acknowledged by writing 234 * the appropriate bit(s) in this register. 235 */ 236 #define ISR_ALL 0x7fff /* all interrupts */ 237 #define ISR_BR 0x4000 /* bus retry occurred */ 238 #define ISR_HBL 0x2000 /* CD heartbeat lost */ 239 #define ISR_LCD 0x1000 /* load CAM command has completed */ 240 #define ISR_PINT 0x0800 /* programmed interrupt from TXpkt.config */ 241 #define ISR_PKTRX 0x0400 /* packet received */ 242 #define ISR_TXDN 0x0200 /* no remaining packets to be transmitted */ 243 #define ISR_TXER 0x0100 /* packet transmission caused error */ 244 #define ISR_TC 0x0080 /* timer complete */ 245 #define ISR_RDE 0x0040 /* receive descriptors exhausted */ 246 #define ISR_RBE 0x0020 /* receive buffers exhausted */ 247 #define ISR_RBAE 0x0010 /* receive buffer area exceeded */ 248 #define ISR_CRC 0x0008 /* CRC tally counter rollover */ 249 #define ISR_FAE 0x0004 /* FAE tally counter rollover */ 250 #define ISR_MP 0x0002 /* MP tally counter rollover */ 251 #define ISR_RFO 0x0001 /* receive FIFO overrun */ 252 253 /* 254 * The second data configuration register allows additional user defined 255 * pins to be controlled. These bits are only available if s_dcr.DCR_EXBUS 256 * is set. 257 */ 258 #define DCR2_EXPO3 0x8000 /* EXUSR3 output */ 259 #define DCR2_EXPO2 0x4000 /* EXUSR2 output */ 260 #define DCR2_EXPO1 0x2000 /* EXUSR1 output */ 261 #define DCR2_EXPO0 0x1000 /* EXUSR0 output */ 262 #define DCR2_HD 0x0800 /* heart beat disable (83934/83936) */ 263 #define DCR2_JD 0x0200 /* TPI jabber timer disable (83934/83936) */ 264 #define DCR2_AUTO 0x0100 /* AUI/TPI auto selection (83934/83936) */ 265 #define DCR2_XWRAP 0x0040 /* TPI transceiver loopback (83934/83936) */ 266 #define DCR2_FD 0x0020 /* full duplex (83936) */ 267 #define DCR2_PHL 0x0010 /* extend HOLD signal by 1/2 clock */ 268 #define DCR2_LRDY 0x0008 /* set latched ready mode */ 269 #define DCR2_PCM 0x0004 /* packet compress on match */ 270 #define DCR2_PCNM 0x0002 /* packet compress on mismatch */ 271 #define DCR2_RJM 0x0001 /* reject on match */ 272