1 /*-
2 * Principal Author: Parag Patel
3 * Copyright (c) 2001
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice unmodified, this list of conditions, and the following
11 * disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * Additional Copyright (c) 2001 by Traakan Software under same licence.
29 * Secondary Author: Matthew Jacob
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 /*
36 * driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
37 */
38
39 /*
40 * Support added for the Marvell 88E1011 (Alaska) 1000/100/10baseTX and
41 * 1000baseSX PHY.
42 * Nathan Binkert <nate@openbsd.org>
43 * Jung-uk Kim <jkim@niksun.com>
44 */
45
46 #include <sys/param.h>
47 #include <sys/systm.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/socket.h>
51 #include <sys/bus.h>
52
53 #include <net/if.h>
54 #include <net/if_var.h>
55 #include <net/if_media.h>
56
57 #include <dev/mii/mii.h>
58 #include <dev/mii/miivar.h>
59 #include "miidevs.h"
60
61 #include <dev/mii/e1000phyreg.h>
62
63 #include "miibus_if.h"
64
65 static int e1000phy_probe(device_t);
66 static int e1000phy_attach(device_t);
67
68 static device_method_t e1000phy_methods[] = {
69 /* device interface */
70 DEVMETHOD(device_probe, e1000phy_probe),
71 DEVMETHOD(device_attach, e1000phy_attach),
72 DEVMETHOD(device_detach, mii_phy_detach),
73 DEVMETHOD(device_shutdown, bus_generic_shutdown),
74 DEVMETHOD_END
75 };
76
77 static devclass_t e1000phy_devclass;
78 static driver_t e1000phy_driver = {
79 "e1000phy",
80 e1000phy_methods,
81 sizeof(struct mii_softc)
82 };
83
84 DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
85
86 static int e1000phy_service(struct mii_softc *, struct mii_data *, int);
87 static void e1000phy_status(struct mii_softc *);
88 static void e1000phy_reset(struct mii_softc *);
89 static int e1000phy_mii_phy_auto(struct mii_softc *, int);
90
91 static const struct mii_phydesc e1000phys[] = {
92 MII_PHY_DESC(MARVELL, E1000),
93 MII_PHY_DESC(MARVELL, E1011),
94 MII_PHY_DESC(MARVELL, E1000_3),
95 MII_PHY_DESC(MARVELL, E1000_5),
96 MII_PHY_DESC(MARVELL, E1111),
97 MII_PHY_DESC(xxMARVELL, E1000),
98 MII_PHY_DESC(xxMARVELL, E1011),
99 MII_PHY_DESC(xxMARVELL, E1000_3),
100 MII_PHY_DESC(xxMARVELL, E1000S),
101 MII_PHY_DESC(xxMARVELL, E1000_5),
102 MII_PHY_DESC(xxMARVELL, E1101),
103 MII_PHY_DESC(xxMARVELL, E3082),
104 MII_PHY_DESC(xxMARVELL, E1112),
105 MII_PHY_DESC(xxMARVELL, E1149),
106 MII_PHY_DESC(xxMARVELL, E1111),
107 MII_PHY_DESC(xxMARVELL, E1116),
108 MII_PHY_DESC(xxMARVELL, E1116R),
109 MII_PHY_DESC(xxMARVELL, E1116R_29),
110 MII_PHY_DESC(xxMARVELL, E1118),
111 MII_PHY_DESC(xxMARVELL, E1145),
112 MII_PHY_DESC(xxMARVELL, E1149R),
113 MII_PHY_DESC(xxMARVELL, E3016),
114 MII_PHY_DESC(xxMARVELL, PHYG65G),
115 MII_PHY_END
116 };
117
118 static const struct mii_phy_funcs e1000phy_funcs = {
119 e1000phy_service,
120 e1000phy_status,
121 e1000phy_reset
122 };
123
124 static int
e1000phy_probe(device_t dev)125 e1000phy_probe(device_t dev)
126 {
127
128 return (mii_phy_dev_probe(dev, e1000phys, BUS_PROBE_DEFAULT));
129 }
130
131 static int
e1000phy_attach(device_t dev)132 e1000phy_attach(device_t dev)
133 {
134 struct mii_softc *sc;
135
136 sc = device_get_softc(dev);
137
138 mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &e1000phy_funcs, 0);
139
140 if (mii_dev_mac_match(dev, "msk") &&
141 (sc->mii_flags & MIIF_MACPRIV0) != 0)
142 sc->mii_flags |= MIIF_PHYPRIV0;
143
144 switch (sc->mii_mpd_model) {
145 case MII_MODEL_xxMARVELL_E1011:
146 case MII_MODEL_xxMARVELL_E1112:
147 if (PHY_READ(sc, E1000_ESSR) & E1000_ESSR_FIBER_LINK)
148 sc->mii_flags |= MIIF_HAVEFIBER;
149 break;
150 case MII_MODEL_xxMARVELL_E1149:
151 case MII_MODEL_xxMARVELL_E1149R:
152 /*
153 * Some 88E1149 PHY's page select is initialized to
154 * point to other bank instead of copper/fiber bank
155 * which in turn resulted in wrong registers were
156 * accessed during PHY operation. It is believed that
157 * page 0 should be used for copper PHY so reinitialize
158 * E1000_EADR to select default copper PHY. If parent
159 * device know the type of PHY(either copper or fiber),
160 * that information should be used to select default
161 * type of PHY.
162 */
163 PHY_WRITE(sc, E1000_EADR, 0);
164 break;
165 }
166
167 PHY_RESET(sc);
168
169 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & sc->mii_capmask;
170 if (sc->mii_capabilities & BMSR_EXTSTAT) {
171 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
172 if ((sc->mii_extcapabilities &
173 (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
174 sc->mii_flags |= MIIF_HAVE_GTCR;
175 }
176 device_printf(dev, " ");
177 mii_phy_add_media(sc);
178 printf("\n");
179
180 MIIBUS_MEDIAINIT(sc->mii_dev);
181 return (0);
182 }
183
184 static void
e1000phy_reset(struct mii_softc * sc)185 e1000phy_reset(struct mii_softc *sc)
186 {
187 uint16_t reg, page;
188
189 reg = PHY_READ(sc, E1000_SCR);
190 if ((sc->mii_flags & MIIF_HAVEFIBER) != 0) {
191 reg &= ~E1000_SCR_AUTO_X_MODE;
192 PHY_WRITE(sc, E1000_SCR, reg);
193 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
194 /* Select 1000BASE-X only mode. */
195 page = PHY_READ(sc, E1000_EADR);
196 PHY_WRITE(sc, E1000_EADR, 2);
197 reg = PHY_READ(sc, E1000_SCR);
198 reg &= ~E1000_SCR_MODE_MASK;
199 reg |= E1000_SCR_MODE_1000BX;
200 PHY_WRITE(sc, E1000_SCR, reg);
201 if ((sc->mii_flags & MIIF_PHYPRIV0) != 0) {
202 /* Set SIGDET polarity low for SFP module. */
203 PHY_WRITE(sc, E1000_EADR, 1);
204 reg = PHY_READ(sc, E1000_SCR);
205 reg |= E1000_SCR_FIB_SIGDET_POLARITY;
206 PHY_WRITE(sc, E1000_SCR, reg);
207 }
208 PHY_WRITE(sc, E1000_EADR, page);
209 }
210 } else {
211 switch (sc->mii_mpd_model) {
212 case MII_MODEL_xxMARVELL_E1111:
213 case MII_MODEL_xxMARVELL_E1112:
214 case MII_MODEL_xxMARVELL_E1116:
215 case MII_MODEL_xxMARVELL_E1116R_29:
216 case MII_MODEL_xxMARVELL_E1118:
217 case MII_MODEL_xxMARVELL_E1149:
218 case MII_MODEL_xxMARVELL_E1149R:
219 case MII_MODEL_xxMARVELL_PHYG65G:
220 /* Disable energy detect mode. */
221 reg &= ~E1000_SCR_EN_DETECT_MASK;
222 reg |= E1000_SCR_AUTO_X_MODE;
223 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
224 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29)
225 reg &= ~E1000_SCR_POWER_DOWN;
226 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
227 break;
228 case MII_MODEL_xxMARVELL_E3082:
229 reg |= (E1000_SCR_AUTO_X_MODE >> 1);
230 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
231 break;
232 case MII_MODEL_xxMARVELL_E3016:
233 reg |= E1000_SCR_AUTO_MDIX;
234 reg &= ~(E1000_SCR_EN_DETECT |
235 E1000_SCR_SCRAMBLER_DISABLE);
236 reg |= E1000_SCR_LPNP;
237 /* XXX Enable class A driver for Yukon FE+ A0. */
238 PHY_WRITE(sc, 0x1C, PHY_READ(sc, 0x1C) | 0x0001);
239 break;
240 default:
241 reg &= ~E1000_SCR_AUTO_X_MODE;
242 reg |= E1000_SCR_ASSERT_CRS_ON_TX;
243 break;
244 }
245 if (sc->mii_mpd_model != MII_MODEL_xxMARVELL_E3016) {
246 /* Auto correction for reversed cable polarity. */
247 reg &= ~E1000_SCR_POLARITY_REVERSAL;
248 }
249 PHY_WRITE(sc, E1000_SCR, reg);
250
251 if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116 ||
252 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1116R_29 ||
253 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149 ||
254 sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1149R) {
255 PHY_WRITE(sc, E1000_EADR, 2);
256 reg = PHY_READ(sc, E1000_SCR);
257 reg |= E1000_SCR_RGMII_POWER_UP;
258 PHY_WRITE(sc, E1000_SCR, reg);
259 PHY_WRITE(sc, E1000_EADR, 0);
260 }
261 }
262
263 switch (sc->mii_mpd_model) {
264 case MII_MODEL_xxMARVELL_E3082:
265 case MII_MODEL_xxMARVELL_E1112:
266 case MII_MODEL_xxMARVELL_E1118:
267 break;
268 case MII_MODEL_xxMARVELL_E1116:
269 case MII_MODEL_xxMARVELL_E1116R_29:
270 page = PHY_READ(sc, E1000_EADR);
271 /* Select page 3, LED control register. */
272 PHY_WRITE(sc, E1000_EADR, 3);
273 PHY_WRITE(sc, E1000_SCR,
274 E1000_SCR_LED_LOS(1) | /* Link/Act */
275 E1000_SCR_LED_INIT(8) | /* 10Mbps */
276 E1000_SCR_LED_STAT1(7) | /* 100Mbps */
277 E1000_SCR_LED_STAT0(7)); /* 1000Mbps */
278 /* Set blink rate. */
279 PHY_WRITE(sc, E1000_IER, E1000_PULSE_DUR(E1000_PULSE_170MS) |
280 E1000_BLINK_RATE(E1000_BLINK_84MS));
281 PHY_WRITE(sc, E1000_EADR, page);
282 break;
283 case MII_MODEL_xxMARVELL_E3016:
284 /* LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED. */
285 PHY_WRITE(sc, 0x16, 0x0B << 8 | 0x05 << 4 | 0x04);
286 /* Integrated register calibration workaround. */
287 PHY_WRITE(sc, 0x1D, 17);
288 PHY_WRITE(sc, 0x1E, 0x3F60);
289 break;
290 default:
291 /* Force TX_CLK to 25MHz clock. */
292 reg = PHY_READ(sc, E1000_ESCR);
293 reg |= E1000_ESCR_TX_CLK_25;
294 PHY_WRITE(sc, E1000_ESCR, reg);
295 break;
296 }
297
298 /* Reset the PHY so all changes take effect. */
299 reg = PHY_READ(sc, E1000_CR);
300 reg |= E1000_CR_RESET;
301 PHY_WRITE(sc, E1000_CR, reg);
302 }
303
304 static int
e1000phy_service(struct mii_softc * sc,struct mii_data * mii,int cmd)305 e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
306 {
307 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
308 uint16_t speed, gig;
309 int reg;
310
311 switch (cmd) {
312 case MII_POLLSTAT:
313 break;
314
315 case MII_MEDIACHG:
316 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
317 e1000phy_mii_phy_auto(sc, ife->ifm_media);
318 break;
319 }
320
321 speed = 0;
322 switch (IFM_SUBTYPE(ife->ifm_media)) {
323 case IFM_1000_T:
324 if ((sc->mii_flags & MIIF_HAVE_GTCR) == 0)
325 return (EINVAL);
326 speed = E1000_CR_SPEED_1000;
327 break;
328 case IFM_1000_SX:
329 if ((sc->mii_extcapabilities &
330 (EXTSR_1000XFDX | EXTSR_1000XHDX)) == 0)
331 return (EINVAL);
332 speed = E1000_CR_SPEED_1000;
333 break;
334 case IFM_100_TX:
335 speed = E1000_CR_SPEED_100;
336 break;
337 case IFM_10_T:
338 speed = E1000_CR_SPEED_10;
339 break;
340 case IFM_NONE:
341 reg = PHY_READ(sc, E1000_CR);
342 PHY_WRITE(sc, E1000_CR,
343 reg | E1000_CR_ISOLATE | E1000_CR_POWER_DOWN);
344 goto done;
345 default:
346 return (EINVAL);
347 }
348
349 if ((ife->ifm_media & IFM_FDX) != 0) {
350 speed |= E1000_CR_FULL_DUPLEX;
351 gig = E1000_1GCR_1000T_FD;
352 } else
353 gig = E1000_1GCR_1000T;
354
355 reg = PHY_READ(sc, E1000_CR);
356 reg &= ~E1000_CR_AUTO_NEG_ENABLE;
357 PHY_WRITE(sc, E1000_CR, reg | E1000_CR_RESET);
358
359 if (IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
360 gig |= E1000_1GCR_MS_ENABLE;
361 if ((ife->ifm_media & IFM_ETH_MASTER) != 0)
362 gig |= E1000_1GCR_MS_VALUE;
363 } else if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0)
364 gig = 0;
365 PHY_WRITE(sc, E1000_1GCR, gig);
366 PHY_WRITE(sc, E1000_AR, E1000_AR_SELECTOR_FIELD);
367 PHY_WRITE(sc, E1000_CR, speed | E1000_CR_RESET);
368 done:
369 break;
370 case MII_TICK:
371 /*
372 * Only used for autonegotiation.
373 */
374 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
375 sc->mii_ticks = 0;
376 break;
377 }
378
379 /*
380 * check for link.
381 * Read the status register twice; BMSR_LINK is latch-low.
382 */
383 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
384 if (reg & BMSR_LINK) {
385 sc->mii_ticks = 0;
386 break;
387 }
388
389 /* Announce link loss right after it happens. */
390 if (sc->mii_ticks++ == 0)
391 break;
392 if (sc->mii_ticks <= sc->mii_anegticks)
393 break;
394
395 sc->mii_ticks = 0;
396 PHY_RESET(sc);
397 e1000phy_mii_phy_auto(sc, ife->ifm_media);
398 break;
399 }
400
401 /* Update the media status. */
402 PHY_STATUS(sc);
403
404 /* Callback if something changed. */
405 mii_phy_update(sc, cmd);
406 return (0);
407 }
408
409 static void
e1000phy_status(struct mii_softc * sc)410 e1000phy_status(struct mii_softc *sc)
411 {
412 struct mii_data *mii = sc->mii_pdata;
413 int bmcr, bmsr, ssr;
414
415 mii->mii_media_status = IFM_AVALID;
416 mii->mii_media_active = IFM_ETHER;
417
418 bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
419 bmcr = PHY_READ(sc, E1000_CR);
420 ssr = PHY_READ(sc, E1000_SSR);
421
422 if (bmsr & E1000_SR_LINK_STATUS)
423 mii->mii_media_status |= IFM_ACTIVE;
424
425 if (bmcr & E1000_CR_LOOPBACK)
426 mii->mii_media_active |= IFM_LOOP;
427
428 if ((bmcr & E1000_CR_AUTO_NEG_ENABLE) != 0 &&
429 (ssr & E1000_SSR_SPD_DPLX_RESOLVED) == 0) {
430 /* Erg, still trying, I guess... */
431 mii->mii_media_active |= IFM_NONE;
432 return;
433 }
434
435 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
436 switch (ssr & E1000_SSR_SPEED) {
437 case E1000_SSR_1000MBS:
438 mii->mii_media_active |= IFM_1000_T;
439 break;
440 case E1000_SSR_100MBS:
441 mii->mii_media_active |= IFM_100_TX;
442 break;
443 case E1000_SSR_10MBS:
444 mii->mii_media_active |= IFM_10_T;
445 break;
446 default:
447 mii->mii_media_active |= IFM_NONE;
448 return;
449 }
450 } else {
451 /*
452 * Some fiber PHY(88E1112) does not seem to set resolved
453 * speed so always assume we've got IFM_1000_SX.
454 */
455 mii->mii_media_active |= IFM_1000_SX;
456 }
457
458 if (ssr & E1000_SSR_DUPLEX) {
459 mii->mii_media_active |= IFM_FDX;
460 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0)
461 mii->mii_media_active |= mii_phy_flowstatus(sc);
462 } else
463 mii->mii_media_active |= IFM_HDX;
464
465 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
466 if (((PHY_READ(sc, E1000_1GSR) | PHY_READ(sc, E1000_1GSR)) &
467 E1000_1GSR_MS_CONFIG_RES) != 0)
468 mii->mii_media_active |= IFM_ETH_MASTER;
469 }
470 }
471
472 static int
e1000phy_mii_phy_auto(struct mii_softc * sc,int media)473 e1000phy_mii_phy_auto(struct mii_softc *sc, int media)
474 {
475 uint16_t reg;
476
477 if ((sc->mii_flags & MIIF_HAVEFIBER) == 0) {
478 reg = PHY_READ(sc, E1000_AR);
479 reg &= ~(E1000_AR_PAUSE | E1000_AR_ASM_DIR);
480 reg |= E1000_AR_10T | E1000_AR_10T_FD |
481 E1000_AR_100TX | E1000_AR_100TX_FD;
482 if ((media & IFM_FLOW) != 0 ||
483 (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
484 reg |= E1000_AR_PAUSE | E1000_AR_ASM_DIR;
485 PHY_WRITE(sc, E1000_AR, reg | E1000_AR_SELECTOR_FIELD);
486 } else
487 PHY_WRITE(sc, E1000_AR, E1000_FA_1000X_FD | E1000_FA_1000X);
488 if ((sc->mii_flags & MIIF_HAVE_GTCR) != 0) {
489 reg = 0;
490 if ((sc->mii_extcapabilities & EXTSR_1000TFDX) != 0)
491 reg |= E1000_1GCR_1000T_FD;
492 if ((sc->mii_extcapabilities & EXTSR_1000THDX) != 0)
493 reg |= E1000_1GCR_1000T;
494 PHY_WRITE(sc, E1000_1GCR, reg);
495 }
496 PHY_WRITE(sc, E1000_CR,
497 E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
498
499 return (EJUSTRETURN);
500 }
501