1 /*-
2 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 /*
32 * Driver for Freescale Fast Ethernet Controller, found on imx-series SoCs among
33 * others. Also works for the ENET Gigibit controller found on imx6 and imx28,
34 * but the driver doesn't currently use any of the ENET advanced features other
35 * than enabling gigabit.
36 *
37 * The interface name 'fec' is already taken by netgraph's Fast Etherchannel
38 * (netgraph/ng_fec.c), so we use 'ffec'.
39 *
40 * Requires an FDT entry with at least these properties:
41 * fec: ethernet@02188000 {
42 * compatible = "fsl,imxNN-fec";
43 * reg = <0x02188000 0x4000>;
44 * interrupts = <150 151>;
45 * phy-mode = "rgmii";
46 * phy-disable-preamble; // optional
47 * };
48 * The second interrupt number is for IEEE-1588, and is not currently used; it
49 * need not be present. phy-mode must be one of: "mii", "rmii", "rgmii".
50 * There is also an optional property, phy-disable-preamble, which if present
51 * will disable the preamble bits, cutting the size of each mdio transaction
52 * (and thus the busy-wait time) in half.
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/bus.h>
58 #include <sys/endian.h>
59 #include <sys/kernel.h>
60 #include <sys/lock.h>
61 #include <sys/malloc.h>
62 #include <sys/mbuf.h>
63 #include <sys/module.h>
64 #include <sys/mutex.h>
65 #include <sys/rman.h>
66 #include <sys/socket.h>
67 #include <sys/sockio.h>
68 #include <sys/sysctl.h>
69
70 #include <machine/bus.h>
71
72 #include <net/bpf.h>
73 #include <net/if.h>
74 #include <net/ethernet.h>
75 #include <net/if_dl.h>
76 #include <net/if_media.h>
77 #include <net/if_types.h>
78 #include <net/if_var.h>
79 #include <net/if_vlan_var.h>
80
81 #include <dev/ffec/if_ffecreg.h>
82 #include <dev/ofw/ofw_bus.h>
83 #include <dev/ofw/ofw_bus_subr.h>
84 #include <dev/mii/mii.h>
85 #include <dev/mii/miivar.h>
86 #include "miibus_if.h"
87
88 /*
89 * There are small differences in the hardware on various SoCs. Not every SoC
90 * we support has its own FECTYPE; most work as GENERIC and only the ones that
91 * need different handling get their own entry. In addition to the types in
92 * this list, there are some flags below that can be ORed into the upper bits.
93 */
94 enum {
95 FECTYPE_NONE,
96 FECTYPE_GENERIC,
97 FECTYPE_IMX53,
98 FECTYPE_IMX6,
99 FECTYPE_MVF,
100 };
101
102 /*
103 * Flags that describe general differences between the FEC hardware in various
104 * SoCs. These are ORed into the FECTYPE enum values.
105 */
106 #define FECTYPE_MASK 0x0000ffff
107 #define FECFLAG_GBE (0x0001 << 16)
108
109 /*
110 * Table of supported FDT compat strings and their associated FECTYPE values.
111 */
112 static struct ofw_compat_data compat_data[] = {
113 {"fsl,imx51-fec", FECTYPE_GENERIC},
114 {"fsl,imx53-fec", FECTYPE_IMX53},
115 {"fsl,imx6q-fec", FECTYPE_IMX6 | FECFLAG_GBE},
116 {"fsl,mvf600-fec", FECTYPE_MVF},
117 {"fsl,mvf-fec", FECTYPE_MVF},
118 {NULL, FECTYPE_NONE},
119 };
120
121 /*
122 * Driver data and defines.
123 */
124 #define RX_DESC_COUNT 64
125 #define RX_DESC_SIZE (sizeof(struct ffec_hwdesc) * RX_DESC_COUNT)
126 #define TX_DESC_COUNT 64
127 #define TX_DESC_SIZE (sizeof(struct ffec_hwdesc) * TX_DESC_COUNT)
128
129 #define WATCHDOG_TIMEOUT_SECS 5
130 #define STATS_HARVEST_INTERVAL 3
131
132 struct ffec_bufmap {
133 struct mbuf *mbuf;
134 bus_dmamap_t map;
135 };
136
137 enum {
138 PHY_CONN_UNKNOWN,
139 PHY_CONN_MII,
140 PHY_CONN_RMII,
141 PHY_CONN_RGMII
142 };
143
144 struct ffec_softc {
145 device_t dev;
146 device_t miibus;
147 struct mii_data * mii_softc;
148 struct ifnet *ifp;
149 int if_flags;
150 struct mtx mtx;
151 struct resource *irq_res;
152 struct resource *mem_res;
153 void * intr_cookie;
154 struct callout ffec_callout;
155 uint8_t phy_conn_type;
156 uint8_t fectype;
157 boolean_t link_is_up;
158 boolean_t is_attached;
159 boolean_t is_detaching;
160 int tx_watchdog_count;
161 int stats_harvest_count;
162
163 bus_dma_tag_t rxdesc_tag;
164 bus_dmamap_t rxdesc_map;
165 struct ffec_hwdesc *rxdesc_ring;
166 bus_addr_t rxdesc_ring_paddr;
167 bus_dma_tag_t rxbuf_tag;
168 struct ffec_bufmap rxbuf_map[RX_DESC_COUNT];
169 uint32_t rx_idx;
170
171 bus_dma_tag_t txdesc_tag;
172 bus_dmamap_t txdesc_map;
173 struct ffec_hwdesc *txdesc_ring;
174 bus_addr_t txdesc_ring_paddr;
175 bus_dma_tag_t txbuf_tag;
176 struct ffec_bufmap txbuf_map[RX_DESC_COUNT];
177 uint32_t tx_idx_head;
178 uint32_t tx_idx_tail;
179 int txcount;
180 };
181
182 #define FFEC_LOCK(sc) mtx_lock(&(sc)->mtx)
183 #define FFEC_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
184 #define FFEC_LOCK_INIT(sc) mtx_init(&(sc)->mtx, \
185 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF)
186 #define FFEC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx);
187 #define FFEC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
188 #define FFEC_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
189
190 static void ffec_init_locked(struct ffec_softc *sc);
191 static void ffec_stop_locked(struct ffec_softc *sc);
192 static void ffec_txstart_locked(struct ffec_softc *sc);
193 static void ffec_txfinish_locked(struct ffec_softc *sc);
194
195 static inline uint16_t
RD2(struct ffec_softc * sc,bus_size_t off)196 RD2(struct ffec_softc *sc, bus_size_t off)
197 {
198
199 return (bus_read_2(sc->mem_res, off));
200 }
201
202 static inline void
WR2(struct ffec_softc * sc,bus_size_t off,uint16_t val)203 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val)
204 {
205
206 bus_write_2(sc->mem_res, off, val);
207 }
208
209 static inline uint32_t
RD4(struct ffec_softc * sc,bus_size_t off)210 RD4(struct ffec_softc *sc, bus_size_t off)
211 {
212
213 return (bus_read_4(sc->mem_res, off));
214 }
215
216 static inline void
WR4(struct ffec_softc * sc,bus_size_t off,uint32_t val)217 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)
218 {
219
220 bus_write_4(sc->mem_res, off, val);
221 }
222
223 static inline uint32_t
next_rxidx(struct ffec_softc * sc,uint32_t curidx)224 next_rxidx(struct ffec_softc *sc, uint32_t curidx)
225 {
226
227 return ((curidx == RX_DESC_COUNT - 1) ? 0 : curidx + 1);
228 }
229
230 static inline uint32_t
next_txidx(struct ffec_softc * sc,uint32_t curidx)231 next_txidx(struct ffec_softc *sc, uint32_t curidx)
232 {
233
234 return ((curidx == TX_DESC_COUNT - 1) ? 0 : curidx + 1);
235 }
236
237 static void
ffec_get1paddr(void * arg,bus_dma_segment_t * segs,int nsegs,int error)238 ffec_get1paddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
239 {
240
241 if (error != 0)
242 return;
243 *(bus_addr_t *)arg = segs[0].ds_addr;
244 }
245
246 static void
ffec_miigasket_setup(struct ffec_softc * sc)247 ffec_miigasket_setup(struct ffec_softc *sc)
248 {
249 uint32_t ifmode;
250
251 /*
252 * We only need the gasket for MII and RMII connections on certain SoCs.
253 */
254
255 switch (sc->fectype & FECTYPE_MASK)
256 {
257 case FECTYPE_IMX53:
258 break;
259 default:
260 return;
261 }
262
263 switch (sc->phy_conn_type)
264 {
265 case PHY_CONN_MII:
266 ifmode = 0;
267 break;
268 case PHY_CONN_RMII:
269 ifmode = FEC_MIIGSK_CFGR_IF_MODE_RMII;
270 break;
271 default:
272 return;
273 }
274
275 /*
276 * Disable the gasket, configure for either MII or RMII, then enable.
277 */
278
279 WR2(sc, FEC_MIIGSK_ENR, 0);
280 while (RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY)
281 continue;
282
283 WR2(sc, FEC_MIIGSK_CFGR, ifmode);
284
285 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);
286 while (!(RD2(sc, FEC_MIIGSK_ENR) & FEC_MIIGSK_ENR_READY))
287 continue;
288 }
289
290 static boolean_t
ffec_miibus_iowait(struct ffec_softc * sc)291 ffec_miibus_iowait(struct ffec_softc *sc)
292 {
293 uint32_t timeout;
294
295 for (timeout = 10000; timeout != 0; --timeout)
296 if (RD4(sc, FEC_IER_REG) & FEC_IER_MII)
297 return (true);
298
299 return (false);
300 }
301
302 static int
ffec_miibus_readreg(device_t dev,int phy,int reg)303 ffec_miibus_readreg(device_t dev, int phy, int reg)
304 {
305 struct ffec_softc *sc;
306 int val;
307
308 sc = device_get_softc(dev);
309
310 WR4(sc, FEC_IER_REG, FEC_IER_MII);
311
312 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |
313 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
314 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
315 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK));
316
317 if (!ffec_miibus_iowait(sc)) {
318 device_printf(dev, "timeout waiting for mii read\n");
319 return (-1); /* All-ones is a symptom of bad mdio. */
320 }
321
322 val = RD4(sc, FEC_MMFR_REG) & FEC_MMFR_DATA_MASK;
323
324 return (val);
325 }
326
327 static int
ffec_miibus_writereg(device_t dev,int phy,int reg,int val)328 ffec_miibus_writereg(device_t dev, int phy, int reg, int val)
329 {
330 struct ffec_softc *sc;
331
332 sc = device_get_softc(dev);
333
334 WR4(sc, FEC_IER_REG, FEC_IER_MII);
335
336 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |
337 FEC_MMFR_ST_VALUE | FEC_MMFR_TA_VALUE |
338 ((phy << FEC_MMFR_PA_SHIFT) & FEC_MMFR_PA_MASK) |
339 ((reg << FEC_MMFR_RA_SHIFT) & FEC_MMFR_RA_MASK) |
340 (val & FEC_MMFR_DATA_MASK));
341
342 if (!ffec_miibus_iowait(sc)) {
343 device_printf(dev, "timeout waiting for mii write\n");
344 return (-1);
345 }
346
347 return (0);
348 }
349
350 static void
ffec_miibus_statchg(device_t dev)351 ffec_miibus_statchg(device_t dev)
352 {
353 struct ffec_softc *sc;
354 struct mii_data *mii;
355 uint32_t ecr, rcr, tcr;
356
357 /*
358 * Called by the MII bus driver when the PHY establishes link to set the
359 * MAC interface registers.
360 */
361
362 sc = device_get_softc(dev);
363
364 FFEC_ASSERT_LOCKED(sc);
365
366 mii = sc->mii_softc;
367
368 if (mii->mii_media_status & IFM_ACTIVE)
369 sc->link_is_up = true;
370 else
371 sc->link_is_up = false;
372
373 ecr = RD4(sc, FEC_ECR_REG) & ~FEC_ECR_SPEED;
374 rcr = RD4(sc, FEC_RCR_REG) & ~(FEC_RCR_RMII_10T | FEC_RCR_RMII_MODE |
375 FEC_RCR_RGMII_EN | FEC_RCR_DRT | FEC_RCR_FCE);
376 tcr = RD4(sc, FEC_TCR_REG) & ~FEC_TCR_FDEN;
377
378 rcr |= FEC_RCR_MII_MODE; /* Must always be on even for R[G]MII. */
379 switch (sc->phy_conn_type) {
380 case PHY_CONN_MII:
381 break;
382 case PHY_CONN_RMII:
383 rcr |= FEC_RCR_RMII_MODE;
384 break;
385 case PHY_CONN_RGMII:
386 rcr |= FEC_RCR_RGMII_EN;
387 break;
388 }
389
390 switch (IFM_SUBTYPE(mii->mii_media_active)) {
391 case IFM_1000_T:
392 case IFM_1000_SX:
393 ecr |= FEC_ECR_SPEED;
394 break;
395 case IFM_100_TX:
396 /* Not-FEC_ECR_SPEED + not-FEC_RCR_RMII_10T means 100TX */
397 break;
398 case IFM_10_T:
399 rcr |= FEC_RCR_RMII_10T;
400 break;
401 case IFM_NONE:
402 sc->link_is_up = false;
403 return;
404 default:
405 sc->link_is_up = false;
406 device_printf(dev, "Unsupported media %u\n",
407 IFM_SUBTYPE(mii->mii_media_active));
408 return;
409 }
410
411 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
412 tcr |= FEC_TCR_FDEN;
413 else
414 rcr |= FEC_RCR_DRT;
415
416 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLOW) != 0)
417 rcr |= FEC_RCR_FCE;
418
419 WR4(sc, FEC_RCR_REG, rcr);
420 WR4(sc, FEC_TCR_REG, tcr);
421 WR4(sc, FEC_ECR_REG, ecr);
422 }
423
424 static void
ffec_media_status(struct ifnet * ifp,struct ifmediareq * ifmr)425 ffec_media_status(struct ifnet * ifp, struct ifmediareq *ifmr)
426 {
427 struct ffec_softc *sc;
428 struct mii_data *mii;
429
430
431 sc = ifp->if_softc;
432 mii = sc->mii_softc;
433 FFEC_LOCK(sc);
434 mii_pollstat(mii);
435 ifmr->ifm_active = mii->mii_media_active;
436 ifmr->ifm_status = mii->mii_media_status;
437 FFEC_UNLOCK(sc);
438 }
439
440 static int
ffec_media_change_locked(struct ffec_softc * sc)441 ffec_media_change_locked(struct ffec_softc *sc)
442 {
443
444 return (mii_mediachg(sc->mii_softc));
445 }
446
447 static int
ffec_media_change(struct ifnet * ifp)448 ffec_media_change(struct ifnet * ifp)
449 {
450 struct ffec_softc *sc;
451 int error;
452
453 sc = ifp->if_softc;
454
455 FFEC_LOCK(sc);
456 error = ffec_media_change_locked(sc);
457 FFEC_UNLOCK(sc);
458 return (error);
459 }
460
ffec_clear_stats(struct ffec_softc * sc)461 static void ffec_clear_stats(struct ffec_softc *sc)
462 {
463
464 WR4(sc, FEC_RMON_R_PACKETS, 0);
465 WR4(sc, FEC_RMON_R_MC_PKT, 0);
466 WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);
467 WR4(sc, FEC_RMON_R_UNDERSIZE, 0);
468 WR4(sc, FEC_RMON_R_OVERSIZE, 0);
469 WR4(sc, FEC_RMON_R_FRAG, 0);
470 WR4(sc, FEC_RMON_R_JAB, 0);
471 WR4(sc, FEC_RMON_T_PACKETS, 0);
472 WR4(sc, FEC_RMON_T_MC_PKT, 0);
473 WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);
474 WR4(sc, FEC_RMON_T_UNDERSIZE, 0);
475 WR4(sc, FEC_RMON_T_OVERSIZE , 0);
476 WR4(sc, FEC_RMON_T_FRAG, 0);
477 WR4(sc, FEC_RMON_T_JAB, 0);
478 WR4(sc, FEC_RMON_T_COL, 0);
479 }
480
481 static void
ffec_harvest_stats(struct ffec_softc * sc)482 ffec_harvest_stats(struct ffec_softc *sc)
483 {
484 struct ifnet *ifp;
485
486 /* We don't need to harvest too often. */
487 if (++sc->stats_harvest_count < STATS_HARVEST_INTERVAL)
488 return;
489
490 /*
491 * Try to avoid harvesting unless the IDLE flag is on, but if it has
492 * been too long just go ahead and do it anyway, the worst that'll
493 * happen is we'll lose a packet count or two as we clear at the end.
494 */
495 if (sc->stats_harvest_count < (2 * STATS_HARVEST_INTERVAL) &&
496 ((RD4(sc, FEC_MIBC_REG) & FEC_MIBC_IDLE) == 0))
497 return;
498
499 sc->stats_harvest_count = 0;
500 ifp = sc->ifp;
501
502 if_inc_counter(ifp, IFCOUNTER_IPACKETS, RD4(sc, FEC_RMON_R_PACKETS));
503 if_inc_counter(ifp, IFCOUNTER_IMCASTS, RD4(sc, FEC_RMON_R_MC_PKT));
504 if_inc_counter(ifp, IFCOUNTER_IERRORS,
505 RD4(sc, FEC_RMON_R_CRC_ALIGN) + RD4(sc, FEC_RMON_R_UNDERSIZE) +
506 RD4(sc, FEC_RMON_R_OVERSIZE) + RD4(sc, FEC_RMON_R_FRAG) +
507 RD4(sc, FEC_RMON_R_JAB));
508
509 if_inc_counter(ifp, IFCOUNTER_OPACKETS, RD4(sc, FEC_RMON_T_PACKETS));
510 if_inc_counter(ifp, IFCOUNTER_OMCASTS, RD4(sc, FEC_RMON_T_MC_PKT));
511 if_inc_counter(ifp, IFCOUNTER_OERRORS,
512 RD4(sc, FEC_RMON_T_CRC_ALIGN) + RD4(sc, FEC_RMON_T_UNDERSIZE) +
513 RD4(sc, FEC_RMON_T_OVERSIZE) + RD4(sc, FEC_RMON_T_FRAG) +
514 RD4(sc, FEC_RMON_T_JAB));
515
516 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, RD4(sc, FEC_RMON_T_COL));
517
518 ffec_clear_stats(sc);
519 }
520
521 static void
ffec_tick(void * arg)522 ffec_tick(void *arg)
523 {
524 struct ffec_softc *sc;
525 struct ifnet *ifp;
526 int link_was_up;
527
528 sc = arg;
529
530 FFEC_ASSERT_LOCKED(sc);
531
532 ifp = sc->ifp;
533
534 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
535 return;
536
537 /*
538 * Typical tx watchdog. If this fires it indicates that we enqueued
539 * packets for output and never got a txdone interrupt for them. Maybe
540 * it's a missed interrupt somehow, just pretend we got one.
541 */
542 if (sc->tx_watchdog_count > 0) {
543 if (--sc->tx_watchdog_count == 0) {
544 ffec_txfinish_locked(sc);
545 }
546 }
547
548 /* Gather stats from hardware counters. */
549 ffec_harvest_stats(sc);
550
551 /* Check the media status. */
552 link_was_up = sc->link_is_up;
553 mii_tick(sc->mii_softc);
554 if (sc->link_is_up && !link_was_up)
555 ffec_txstart_locked(sc);
556
557 /* Schedule another check one second from now. */
558 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
559 }
560
561 inline static uint32_t
ffec_setup_txdesc(struct ffec_softc * sc,int idx,bus_addr_t paddr,uint32_t len)562 ffec_setup_txdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr,
563 uint32_t len)
564 {
565 uint32_t nidx;
566 uint32_t flags;
567
568 nidx = next_txidx(sc, idx);
569
570 /* Addr/len 0 means we're clearing the descriptor after xmit done. */
571 if (paddr == 0 || len == 0) {
572 flags = 0;
573 --sc->txcount;
574 } else {
575 flags = FEC_TXDESC_READY | FEC_TXDESC_L | FEC_TXDESC_TC;
576 ++sc->txcount;
577 }
578 if (nidx == 0)
579 flags |= FEC_TXDESC_WRAP;
580
581 /*
582 * The hardware requires 32-bit physical addresses. We set up the dma
583 * tag to indicate that, so the cast to uint32_t should never lose
584 * significant bits.
585 */
586 sc->txdesc_ring[idx].buf_paddr = (uint32_t)paddr;
587 sc->txdesc_ring[idx].flags_len = flags | len; /* Must be set last! */
588
589 return (nidx);
590 }
591
592 static int
ffec_setup_txbuf(struct ffec_softc * sc,int idx,struct mbuf ** mp)593 ffec_setup_txbuf(struct ffec_softc *sc, int idx, struct mbuf **mp)
594 {
595 struct mbuf * m;
596 int error, nsegs;
597 struct bus_dma_segment seg;
598
599 if ((m = m_defrag(*mp, M_NOWAIT)) == NULL)
600 return (ENOMEM);
601 *mp = m;
602
603 error = bus_dmamap_load_mbuf_sg(sc->txbuf_tag, sc->txbuf_map[idx].map,
604 m, &seg, &nsegs, 0);
605 if (error != 0) {
606 return (ENOMEM);
607 }
608 bus_dmamap_sync(sc->txbuf_tag, sc->txbuf_map[idx].map,
609 BUS_DMASYNC_PREWRITE);
610
611 sc->txbuf_map[idx].mbuf = m;
612 ffec_setup_txdesc(sc, idx, seg.ds_addr, seg.ds_len);
613
614 return (0);
615
616 }
617
618 static void
ffec_txstart_locked(struct ffec_softc * sc)619 ffec_txstart_locked(struct ffec_softc *sc)
620 {
621 struct ifnet *ifp;
622 struct mbuf *m;
623 int enqueued;
624
625 FFEC_ASSERT_LOCKED(sc);
626
627 if (!sc->link_is_up)
628 return;
629
630 ifp = sc->ifp;
631
632 if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
633 return;
634
635 enqueued = 0;
636
637 for (;;) {
638 if (sc->txcount == (TX_DESC_COUNT-1)) {
639 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
640 break;
641 }
642 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
643 if (m == NULL)
644 break;
645 if (ffec_setup_txbuf(sc, sc->tx_idx_head, &m) != 0) {
646 IFQ_DRV_PREPEND(&ifp->if_snd, m);
647 break;
648 }
649 BPF_MTAP(ifp, m);
650 sc->tx_idx_head = next_txidx(sc, sc->tx_idx_head);
651 ++enqueued;
652 }
653
654 if (enqueued != 0) {
655 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
656 WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);
657 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
658 sc->tx_watchdog_count = WATCHDOG_TIMEOUT_SECS;
659 }
660 }
661
662 static void
ffec_txstart(struct ifnet * ifp)663 ffec_txstart(struct ifnet *ifp)
664 {
665 struct ffec_softc *sc = ifp->if_softc;
666
667 FFEC_LOCK(sc);
668 ffec_txstart_locked(sc);
669 FFEC_UNLOCK(sc);
670 }
671
672 static void
ffec_txfinish_locked(struct ffec_softc * sc)673 ffec_txfinish_locked(struct ffec_softc *sc)
674 {
675 struct ifnet *ifp;
676 struct ffec_hwdesc *desc;
677 struct ffec_bufmap *bmap;
678 boolean_t retired_buffer;
679
680 FFEC_ASSERT_LOCKED(sc);
681
682 /* XXX Can't set PRE|POST right now, but we need both. */
683 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREREAD);
684 bus_dmamap_sync(sc->txdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTREAD);
685 ifp = sc->ifp;
686 retired_buffer = false;
687 while (sc->tx_idx_tail != sc->tx_idx_head) {
688 desc = &sc->txdesc_ring[sc->tx_idx_tail];
689 if (desc->flags_len & FEC_TXDESC_READY)
690 break;
691 retired_buffer = true;
692 bmap = &sc->txbuf_map[sc->tx_idx_tail];
693 bus_dmamap_sync(sc->txbuf_tag, bmap->map,
694 BUS_DMASYNC_POSTWRITE);
695 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
696 m_freem(bmap->mbuf);
697 bmap->mbuf = NULL;
698 ffec_setup_txdesc(sc, sc->tx_idx_tail, 0, 0);
699 sc->tx_idx_tail = next_txidx(sc, sc->tx_idx_tail);
700 }
701
702 /*
703 * If we retired any buffers, there will be open tx slots available in
704 * the descriptor ring, go try to start some new output.
705 */
706 if (retired_buffer) {
707 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
708 ffec_txstart_locked(sc);
709 }
710
711 /* If there are no buffers outstanding, muzzle the watchdog. */
712 if (sc->tx_idx_tail == sc->tx_idx_head) {
713 sc->tx_watchdog_count = 0;
714 }
715 }
716
717 inline static uint32_t
ffec_setup_rxdesc(struct ffec_softc * sc,int idx,bus_addr_t paddr)718 ffec_setup_rxdesc(struct ffec_softc *sc, int idx, bus_addr_t paddr)
719 {
720 uint32_t nidx;
721
722 /*
723 * The hardware requires 32-bit physical addresses. We set up the dma
724 * tag to indicate that, so the cast to uint32_t should never lose
725 * significant bits.
726 */
727 nidx = next_rxidx(sc, idx);
728 sc->rxdesc_ring[idx].buf_paddr = (uint32_t)paddr;
729 sc->rxdesc_ring[idx].flags_len = FEC_RXDESC_EMPTY |
730 ((nidx == 0) ? FEC_RXDESC_WRAP : 0);
731
732 return (nidx);
733 }
734
735 static int
ffec_setup_rxbuf(struct ffec_softc * sc,int idx,struct mbuf * m)736 ffec_setup_rxbuf(struct ffec_softc *sc, int idx, struct mbuf * m)
737 {
738 int error, nsegs;
739 struct bus_dma_segment seg;
740
741 /*
742 * We need to leave at least ETHER_ALIGN bytes free at the beginning of
743 * the buffer to allow the data to be re-aligned after receiving it (by
744 * copying it backwards ETHER_ALIGN bytes in the same buffer). We also
745 * have to ensure that the beginning of the buffer is aligned to the
746 * hardware's requirements.
747 */
748 m_adj(m, roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN));
749
750 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
751 m, &seg, &nsegs, 0);
752 if (error != 0) {
753 return (error);
754 }
755
756 bus_dmamap_sync(sc->rxbuf_tag, sc->rxbuf_map[idx].map,
757 BUS_DMASYNC_PREREAD);
758
759 sc->rxbuf_map[idx].mbuf = m;
760 ffec_setup_rxdesc(sc, idx, seg.ds_addr);
761
762 return (0);
763 }
764
765 static struct mbuf *
ffec_alloc_mbufcl(struct ffec_softc * sc)766 ffec_alloc_mbufcl(struct ffec_softc *sc)
767 {
768 struct mbuf *m;
769
770 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
771 m->m_pkthdr.len = m->m_len = m->m_ext.ext_size;
772
773 return (m);
774 }
775
776 static void
ffec_rxfinish_onebuf(struct ffec_softc * sc,int len)777 ffec_rxfinish_onebuf(struct ffec_softc *sc, int len)
778 {
779 struct mbuf *m, *newmbuf;
780 struct ffec_bufmap *bmap;
781 uint8_t *dst, *src;
782 int error;
783
784 /*
785 * First try to get a new mbuf to plug into this slot in the rx ring.
786 * If that fails, drop the current packet and recycle the current
787 * mbuf, which is still mapped and loaded.
788 */
789 if ((newmbuf = ffec_alloc_mbufcl(sc)) == NULL) {
790 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, 1);
791 ffec_setup_rxdesc(sc, sc->rx_idx,
792 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
793 return;
794 }
795
796 /*
797 * Unfortunately, the protocol headers need to be aligned on a 32-bit
798 * boundary for the upper layers. The hardware requires receive
799 * buffers to be 16-byte aligned. The ethernet header is 14 bytes,
800 * leaving the protocol header unaligned. We used m_adj() after
801 * allocating the buffer to leave empty space at the start of the
802 * buffer, now we'll use the alignment agnostic bcopy() routine to
803 * shuffle all the data backwards 2 bytes and adjust m_data.
804 *
805 * XXX imx6 hardware is able to do this 2-byte alignment by setting the
806 * SHIFT16 bit in the RACC register. Older hardware doesn't have that
807 * feature, but for them could we speed this up by copying just the
808 * protocol headers into their own small mbuf then chaining the cluster
809 * to it? That way we'd only need to copy like 64 bytes or whatever
810 * the biggest header is, instead of the whole 1530ish-byte frame.
811 */
812
813 FFEC_UNLOCK(sc);
814
815 bmap = &sc->rxbuf_map[sc->rx_idx];
816 len -= ETHER_CRC_LEN;
817 bus_dmamap_sync(sc->rxbuf_tag, bmap->map, BUS_DMASYNC_POSTREAD);
818 bus_dmamap_unload(sc->rxbuf_tag, bmap->map);
819 m = bmap->mbuf;
820 bmap->mbuf = NULL;
821 m->m_len = len;
822 m->m_pkthdr.len = len;
823 m->m_pkthdr.rcvif = sc->ifp;
824
825 src = mtod(m, uint8_t*);
826 dst = src - ETHER_ALIGN;
827 bcopy(src, dst, len);
828 m->m_data = dst;
829 sc->ifp->if_input(sc->ifp, m);
830
831 FFEC_LOCK(sc);
832
833 if ((error = ffec_setup_rxbuf(sc, sc->rx_idx, newmbuf)) != 0) {
834 device_printf(sc->dev, "ffec_setup_rxbuf error %d\n", error);
835 /* XXX Now what? We've got a hole in the rx ring. */
836 }
837
838 }
839
840 static void
ffec_rxfinish_locked(struct ffec_softc * sc)841 ffec_rxfinish_locked(struct ffec_softc *sc)
842 {
843 struct ffec_hwdesc *desc;
844 int len;
845 boolean_t produced_empty_buffer;
846
847 FFEC_ASSERT_LOCKED(sc);
848
849 /* XXX Can't set PRE|POST right now, but we need both. */
850 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_PREREAD);
851 bus_dmamap_sync(sc->rxdesc_tag, sc->rxdesc_map, BUS_DMASYNC_POSTREAD);
852 produced_empty_buffer = false;
853 for (;;) {
854 desc = &sc->rxdesc_ring[sc->rx_idx];
855 if (desc->flags_len & FEC_RXDESC_EMPTY)
856 break;
857 produced_empty_buffer = true;
858 len = (desc->flags_len & FEC_RXDESC_LEN_MASK);
859 if (len < 64) {
860 /*
861 * Just recycle the descriptor and continue. .
862 */
863 ffec_setup_rxdesc(sc, sc->rx_idx,
864 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
865 } else if ((desc->flags_len & FEC_RXDESC_L) == 0) {
866 /*
867 * The entire frame is not in this buffer. Impossible.
868 * Recycle the descriptor and continue.
869 *
870 * XXX what's the right way to handle this? Probably we
871 * should stop/init the hardware because this should
872 * just really never happen when we have buffers bigger
873 * than the maximum frame size.
874 */
875 device_printf(sc->dev,
876 "fec_rxfinish: received frame without LAST bit set");
877 ffec_setup_rxdesc(sc, sc->rx_idx,
878 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
879 } else if (desc->flags_len & FEC_RXDESC_ERROR_BITS) {
880 /*
881 * Something went wrong with receiving the frame, we
882 * don't care what (the hardware has counted the error
883 * in the stats registers already), we just reuse the
884 * same mbuf, which is still dma-mapped, by resetting
885 * the rx descriptor.
886 */
887 ffec_setup_rxdesc(sc, sc->rx_idx,
888 sc->rxdesc_ring[sc->rx_idx].buf_paddr);
889 } else {
890 /*
891 * Normal case: a good frame all in one buffer.
892 */
893 ffec_rxfinish_onebuf(sc, len);
894 }
895 sc->rx_idx = next_rxidx(sc, sc->rx_idx);
896 }
897
898 if (produced_empty_buffer) {
899 bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_PREWRITE);
900 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
901 bus_dmamap_sync(sc->rxdesc_tag, sc->txdesc_map, BUS_DMASYNC_POSTWRITE);
902 }
903 }
904
905 static void
ffec_get_hwaddr(struct ffec_softc * sc,uint8_t * hwaddr)906 ffec_get_hwaddr(struct ffec_softc *sc, uint8_t *hwaddr)
907 {
908 uint32_t palr, paur, rnd;
909
910 /*
911 * Try to recover a MAC address from the running hardware. If there's
912 * something non-zero there, assume the bootloader did the right thing
913 * and just use it.
914 *
915 * Otherwise, set the address to a convenient locally assigned address,
916 * 'bsd' + random 24 low-order bits. 'b' is 0x62, which has the locally
917 * assigned bit set, and the broadcast/multicast bit clear.
918 */
919 palr = RD4(sc, FEC_PALR_REG);
920 paur = RD4(sc, FEC_PAUR_REG) & FEC_PAUR_PADDR2_MASK;
921 if ((palr | paur) != 0) {
922 hwaddr[0] = palr >> 24;
923 hwaddr[1] = palr >> 16;
924 hwaddr[2] = palr >> 8;
925 hwaddr[3] = palr >> 0;
926 hwaddr[4] = paur >> 24;
927 hwaddr[5] = paur >> 16;
928 } else {
929 rnd = arc4random() & 0x00ffffff;
930 hwaddr[0] = 'b';
931 hwaddr[1] = 's';
932 hwaddr[2] = 'd';
933 hwaddr[3] = rnd >> 16;
934 hwaddr[4] = rnd >> 8;
935 hwaddr[5] = rnd >> 0;
936 }
937
938 if (bootverbose) {
939 device_printf(sc->dev,
940 "MAC address %02x:%02x:%02x:%02x:%02x:%02x:\n",
941 hwaddr[0], hwaddr[1], hwaddr[2],
942 hwaddr[3], hwaddr[4], hwaddr[5]);
943 }
944 }
945
946 static void
ffec_setup_rxfilter(struct ffec_softc * sc)947 ffec_setup_rxfilter(struct ffec_softc *sc)
948 {
949 struct ifnet *ifp;
950 struct ifmultiaddr *ifma;
951 uint8_t *eaddr;
952 uint32_t crc;
953 uint64_t ghash, ihash;
954
955 FFEC_ASSERT_LOCKED(sc);
956
957 ifp = sc->ifp;
958
959 /*
960 * Set the multicast (group) filter hash.
961 */
962 if ((ifp->if_flags & IFF_ALLMULTI))
963 ghash = 0xffffffffffffffffLLU;
964 else {
965 ghash = 0;
966 if_maddr_rlock(ifp);
967 TAILQ_FOREACH(ifma, &sc->ifp->if_multiaddrs, ifma_link) {
968 if (ifma->ifma_addr->sa_family != AF_LINK)
969 continue;
970 /* 6 bits from MSB in LE CRC32 are used for hash. */
971 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
972 ifma->ifma_addr), ETHER_ADDR_LEN);
973 ghash |= 1LLU << (((uint8_t *)&crc)[3] >> 2);
974 }
975 if_maddr_runlock(ifp);
976 }
977 WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));
978 WR4(sc, FEC_GALR_REG, (uint32_t)ghash);
979
980 /*
981 * Set the individual address filter hash.
982 *
983 * XXX Is 0 the right value when promiscuous is off? This hw feature
984 * seems to support the concept of MAC address aliases, does such a
985 * thing even exist?
986 */
987 if ((ifp->if_flags & IFF_PROMISC))
988 ihash = 0xffffffffffffffffLLU;
989 else {
990 ihash = 0;
991 }
992 WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));
993 WR4(sc, FEC_IALR_REG, (uint32_t)ihash);
994
995 /*
996 * Set the primary address.
997 */
998 eaddr = IF_LLADDR(ifp);
999 WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |
1000 (eaddr[2] << 8) | eaddr[3]);
1001 WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));
1002 }
1003
1004 static void
ffec_stop_locked(struct ffec_softc * sc)1005 ffec_stop_locked(struct ffec_softc *sc)
1006 {
1007 struct ifnet *ifp;
1008 struct ffec_hwdesc *desc;
1009 struct ffec_bufmap *bmap;
1010 int idx;
1011
1012 FFEC_ASSERT_LOCKED(sc);
1013
1014 ifp = sc->ifp;
1015 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1016 sc->tx_watchdog_count = 0;
1017 sc->stats_harvest_count = 0;
1018
1019 /*
1020 * Stop the hardware, mask all interrupts, and clear all current
1021 * interrupt status bits.
1022 */
1023 WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);
1024 WR4(sc, FEC_IEM_REG, 0x00000000);
1025 WR4(sc, FEC_IER_REG, 0xffffffff);
1026
1027 /*
1028 * Stop the media-check callout. Do not use callout_drain() because
1029 * we're holding a mutex the callout acquires, and if it's currently
1030 * waiting to acquire it, we'd deadlock. If it is waiting now, the
1031 * ffec_tick() routine will return without doing anything when it sees
1032 * that IFF_DRV_RUNNING is not set, so avoiding callout_drain() is safe.
1033 */
1034 callout_stop(&sc->ffec_callout);
1035
1036 /*
1037 * Discard all untransmitted buffers. Each buffer is simply freed;
1038 * it's as if the bits were transmitted and then lost on the wire.
1039 *
1040 * XXX Is this right? Or should we use IFQ_DRV_PREPEND() to put them
1041 * back on the queue for when we get restarted later?
1042 */
1043 idx = sc->tx_idx_tail;
1044 while (idx != sc->tx_idx_head) {
1045 desc = &sc->txdesc_ring[idx];
1046 bmap = &sc->txbuf_map[idx];
1047 if (desc->buf_paddr != 0) {
1048 bus_dmamap_unload(sc->txbuf_tag, bmap->map);
1049 m_freem(bmap->mbuf);
1050 bmap->mbuf = NULL;
1051 ffec_setup_txdesc(sc, idx, 0, 0);
1052 }
1053 idx = next_txidx(sc, idx);
1054 }
1055
1056 /*
1057 * Discard all unprocessed receive buffers. This amounts to just
1058 * pretending that nothing ever got received into them. We reuse the
1059 * mbuf already mapped for each desc, simply turning the EMPTY flags
1060 * back on so they'll get reused when we start up again.
1061 */
1062 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1063 desc = &sc->rxdesc_ring[idx];
1064 ffec_setup_rxdesc(sc, idx, desc->buf_paddr);
1065 }
1066 }
1067
1068 static void
ffec_init_locked(struct ffec_softc * sc)1069 ffec_init_locked(struct ffec_softc *sc)
1070 {
1071 struct ifnet *ifp = sc->ifp;
1072 uint32_t maxbuf, maxfl, regval;
1073
1074 FFEC_ASSERT_LOCKED(sc);
1075
1076 /*
1077 * The hardware has a limit of 0x7ff as the max frame length (see
1078 * comments for MRBR below), and we use mbuf clusters as receive
1079 * buffers, and we currently are designed to receive an entire frame
1080 * into a single buffer.
1081 *
1082 * We start with a MCLBYTES-sized cluster, but we have to offset into
1083 * the buffer by ETHER_ALIGN to make room for post-receive re-alignment,
1084 * and then that value has to be rounded up to the hardware's DMA
1085 * alignment requirements, so all in all our buffer is that much smaller
1086 * than MCLBYTES.
1087 *
1088 * The resulting value is used as the frame truncation length and the
1089 * max buffer receive buffer size for now. It'll become more complex
1090 * when we support jumbo frames and receiving fragments of them into
1091 * separate buffers.
1092 */
1093 maxbuf = MCLBYTES - roundup(ETHER_ALIGN, FEC_RXBUF_ALIGN);
1094 maxfl = min(maxbuf, 0x7ff);
1095
1096 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1097 return;
1098
1099 /* Mask all interrupts and clear all current interrupt status bits. */
1100 WR4(sc, FEC_IEM_REG, 0x00000000);
1101 WR4(sc, FEC_IER_REG, 0xffffffff);
1102
1103 /*
1104 * Go set up palr/puar, galr/gaur, ialr/iaur.
1105 */
1106 ffec_setup_rxfilter(sc);
1107
1108 /*
1109 * TFWR - Transmit FIFO watermark register.
1110 *
1111 * Set the transmit fifo watermark register to "store and forward" mode
1112 * and also set a threshold of 128 bytes in the fifo before transmission
1113 * of a frame begins (to avoid dma underruns). Recent FEC hardware
1114 * supports STRFWD and when that bit is set, the watermark level in the
1115 * low bits is ignored. Older hardware doesn't have STRFWD, but writing
1116 * to that bit is innocuous, and the TWFR bits get used instead.
1117 */
1118 WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);
1119
1120 /* RCR - Receive control register.
1121 *
1122 * Set max frame length + clean out anything left from u-boot.
1123 */
1124 WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));
1125
1126 /*
1127 * TCR - Transmit control register.
1128 *
1129 * Clean out anything left from u-boot. Any necessary values are set in
1130 * ffec_miibus_statchg() based on the media type.
1131 */
1132 WR4(sc, FEC_TCR_REG, 0);
1133
1134 /*
1135 * OPD - Opcode/pause duration.
1136 *
1137 * XXX These magic numbers come from u-boot.
1138 */
1139 WR4(sc, FEC_OPD_REG, 0x00010020);
1140
1141 /*
1142 * FRSR - Fifo receive start register.
1143 *
1144 * This register does not exist on imx6, it is present on earlier
1145 * hardware. The u-boot code sets this to a non-default value that's 32
1146 * bytes larger than the default, with no clue as to why. The default
1147 * value should work fine, so there's no code to init it here.
1148 */
1149
1150 /*
1151 * MRBR - Max RX buffer size.
1152 *
1153 * Note: For hardware prior to imx6 this value cannot exceed 0x07ff,
1154 * but the datasheet says no such thing for imx6. On the imx6, setting
1155 * this to 2K without setting EN1588 resulted in a crazy runaway
1156 * receive loop in the hardware, where every rx descriptor in the ring
1157 * had its EMPTY flag cleared, no completion or error flags set, and a
1158 * length of zero. I think maybe you can only exceed it when EN1588 is
1159 * set, like maybe that's what enables jumbo frames, because in general
1160 * the EN1588 flag seems to be the "enable new stuff" vs. "be legacy-
1161 * compatible" flag.
1162 */
1163 WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);
1164
1165 /*
1166 * FTRL - Frame truncation length.
1167 *
1168 * Must be greater than or equal to the value set in FEC_RCR_MAXFL.
1169 */
1170 WR4(sc, FEC_FTRL_REG, maxfl);
1171
1172 /*
1173 * RDSR / TDSR descriptor ring pointers.
1174 *
1175 * When we turn on ECR_ETHEREN at the end, the hardware zeroes its
1176 * internal current descriptor index values for both rings, so we zero
1177 * our index values as well.
1178 */
1179 sc->rx_idx = 0;
1180 sc->tx_idx_head = sc->tx_idx_tail = 0;
1181 sc->txcount = 0;
1182 WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);
1183 WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);
1184
1185 /*
1186 * EIM - interrupt mask register.
1187 *
1188 * We always enable the same set of interrupts while running; unlike
1189 * some drivers there's no need to change the mask on the fly depending
1190 * on what operations are in progress.
1191 */
1192 WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);
1193
1194 /*
1195 * MIBC - MIB control (hardware stats).
1196 */
1197 regval = RD4(sc, FEC_MIBC_REG);
1198 WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);
1199 ffec_clear_stats(sc);
1200 WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);
1201
1202 /*
1203 * ECR - Ethernet control register.
1204 *
1205 * This must happen after all the other config registers are set. If
1206 * we're running on little-endian hardware, also set the flag for byte-
1207 * swapping descriptor ring entries. This flag doesn't exist on older
1208 * hardware, but it can be safely set -- the bit position it occupies
1209 * was unused.
1210 */
1211 regval = RD4(sc, FEC_ECR_REG);
1212 #if _BYTE_ORDER == _LITTLE_ENDIAN
1213 regval |= FEC_ECR_DBSWP;
1214 #endif
1215 regval |= FEC_ECR_ETHEREN;
1216 WR4(sc, FEC_ECR_REG, regval);
1217
1218 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1219
1220 /*
1221 * Call mii_mediachg() which will call back into ffec_miibus_statchg() to
1222 * set up the remaining config registers based on the current media.
1223 */
1224 mii_mediachg(sc->mii_softc);
1225 callout_reset(&sc->ffec_callout, hz, ffec_tick, sc);
1226
1227 /*
1228 * Tell the hardware that receive buffers are available. They were made
1229 * available in ffec_attach() or ffec_stop().
1230 */
1231 WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);
1232 }
1233
1234 static void
ffec_init(void * if_softc)1235 ffec_init(void *if_softc)
1236 {
1237 struct ffec_softc *sc = if_softc;
1238
1239 FFEC_LOCK(sc);
1240 ffec_init_locked(sc);
1241 FFEC_UNLOCK(sc);
1242 }
1243
1244 static void
ffec_intr(void * arg)1245 ffec_intr(void *arg)
1246 {
1247 struct ffec_softc *sc;
1248 uint32_t ier;
1249
1250 sc = arg;
1251
1252 FFEC_LOCK(sc);
1253
1254 ier = RD4(sc, FEC_IER_REG);
1255
1256 if (ier & FEC_IER_TXF) {
1257 WR4(sc, FEC_IER_REG, FEC_IER_TXF);
1258 ffec_txfinish_locked(sc);
1259 }
1260
1261 if (ier & FEC_IER_RXF) {
1262 WR4(sc, FEC_IER_REG, FEC_IER_RXF);
1263 ffec_rxfinish_locked(sc);
1264 }
1265
1266 /*
1267 * We actually don't care about most errors, because the hardware copes
1268 * with them just fine, discarding the incoming bad frame, or forcing a
1269 * bad CRC onto an outgoing bad frame, and counting the errors in the
1270 * stats registers. The one that really matters is EBERR (DMA bus
1271 * error) because the hardware automatically clears ECR[ETHEREN] and we
1272 * have to restart it here. It should never happen.
1273 */
1274 if (ier & FEC_IER_EBERR) {
1275 WR4(sc, FEC_IER_REG, FEC_IER_EBERR);
1276 device_printf(sc->dev,
1277 "Ethernet DMA error, restarting controller.\n");
1278 ffec_stop_locked(sc);
1279 ffec_init_locked(sc);
1280 }
1281
1282 FFEC_UNLOCK(sc);
1283
1284 }
1285
1286 static int
ffec_ioctl(struct ifnet * ifp,u_long cmd,caddr_t data)1287 ffec_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1288 {
1289 struct ffec_softc *sc;
1290 struct mii_data *mii;
1291 struct ifreq *ifr;
1292 int mask, error;
1293
1294 sc = ifp->if_softc;
1295 ifr = (struct ifreq *)data;
1296
1297 error = 0;
1298 switch (cmd) {
1299 case SIOCSIFFLAGS:
1300 FFEC_LOCK(sc);
1301 if (ifp->if_flags & IFF_UP) {
1302 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1303 if ((ifp->if_flags ^ sc->if_flags) &
1304 (IFF_PROMISC | IFF_ALLMULTI))
1305 ffec_setup_rxfilter(sc);
1306 } else {
1307 if (!sc->is_detaching)
1308 ffec_init_locked(sc);
1309 }
1310 } else {
1311 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1312 ffec_stop_locked(sc);
1313 }
1314 sc->if_flags = ifp->if_flags;
1315 FFEC_UNLOCK(sc);
1316 break;
1317
1318 case SIOCADDMULTI:
1319 case SIOCDELMULTI:
1320 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1321 FFEC_LOCK(sc);
1322 ffec_setup_rxfilter(sc);
1323 FFEC_UNLOCK(sc);
1324 }
1325 break;
1326
1327 case SIOCSIFMEDIA:
1328 case SIOCGIFMEDIA:
1329 mii = sc->mii_softc;
1330 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1331 break;
1332
1333 case SIOCSIFCAP:
1334 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
1335 if (mask & IFCAP_VLAN_MTU) {
1336 /* No work to do except acknowledge the change took. */
1337 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1338 }
1339 break;
1340
1341 default:
1342 error = ether_ioctl(ifp, cmd, data);
1343 break;
1344 }
1345
1346 return (error);
1347 }
1348
1349 static int
ffec_detach(device_t dev)1350 ffec_detach(device_t dev)
1351 {
1352 struct ffec_softc *sc;
1353 bus_dmamap_t map;
1354 int idx;
1355
1356 /*
1357 * NB: This function can be called internally to unwind a failure to
1358 * attach. Make sure a resource got allocated/created before destroying.
1359 */
1360
1361 sc = device_get_softc(dev);
1362
1363 if (sc->is_attached) {
1364 FFEC_LOCK(sc);
1365 sc->is_detaching = true;
1366 ffec_stop_locked(sc);
1367 FFEC_UNLOCK(sc);
1368 callout_drain(&sc->ffec_callout);
1369 ether_ifdetach(sc->ifp);
1370 }
1371
1372 /* XXX no miibus detach? */
1373
1374 /* Clean up RX DMA resources and free mbufs. */
1375 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1376 if ((map = sc->rxbuf_map[idx].map) != NULL) {
1377 bus_dmamap_unload(sc->rxbuf_tag, map);
1378 bus_dmamap_destroy(sc->rxbuf_tag, map);
1379 m_freem(sc->rxbuf_map[idx].mbuf);
1380 }
1381 }
1382 if (sc->rxbuf_tag != NULL)
1383 bus_dma_tag_destroy(sc->rxbuf_tag);
1384 if (sc->rxdesc_map != NULL) {
1385 bus_dmamap_unload(sc->rxdesc_tag, sc->rxdesc_map);
1386 bus_dmamap_destroy(sc->rxdesc_tag, sc->rxdesc_map);
1387 }
1388 if (sc->rxdesc_tag != NULL)
1389 bus_dma_tag_destroy(sc->rxdesc_tag);
1390
1391 /* Clean up TX DMA resources. */
1392 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1393 if ((map = sc->txbuf_map[idx].map) != NULL) {
1394 /* TX maps are already unloaded. */
1395 bus_dmamap_destroy(sc->txbuf_tag, map);
1396 }
1397 }
1398 if (sc->txbuf_tag != NULL)
1399 bus_dma_tag_destroy(sc->txbuf_tag);
1400 if (sc->txdesc_map != NULL) {
1401 bus_dmamap_unload(sc->txdesc_tag, sc->txdesc_map);
1402 bus_dmamap_destroy(sc->txdesc_tag, sc->txdesc_map);
1403 }
1404 if (sc->txdesc_tag != NULL)
1405 bus_dma_tag_destroy(sc->txdesc_tag);
1406
1407 /* Release bus resources. */
1408 if (sc->intr_cookie)
1409 bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
1410
1411 if (sc->irq_res != NULL)
1412 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
1413
1414 if (sc->mem_res != NULL)
1415 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
1416
1417 FFEC_LOCK_DESTROY(sc);
1418 return (0);
1419 }
1420
1421 static int
ffec_attach(device_t dev)1422 ffec_attach(device_t dev)
1423 {
1424 struct ffec_softc *sc;
1425 struct ifnet *ifp = NULL;
1426 struct mbuf *m;
1427 phandle_t ofw_node;
1428 int error, rid;
1429 uint8_t eaddr[ETHER_ADDR_LEN];
1430 char phy_conn_name[32];
1431 uint32_t idx, mscr;
1432
1433 sc = device_get_softc(dev);
1434 sc->dev = dev;
1435
1436 FFEC_LOCK_INIT(sc);
1437
1438 /*
1439 * There are differences in the implementation and features of the FEC
1440 * hardware on different SoCs, so figure out what type we are.
1441 */
1442 sc->fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1443
1444 /*
1445 * We have to be told what kind of electrical connection exists between
1446 * the MAC and PHY or we can't operate correctly.
1447 */
1448 if ((ofw_node = ofw_bus_get_node(dev)) == -1) {
1449 device_printf(dev, "Impossible: Can't find ofw bus node\n");
1450 error = ENXIO;
1451 goto out;
1452 }
1453 if (OF_searchprop(ofw_node, "phy-mode",
1454 phy_conn_name, sizeof(phy_conn_name)) != -1) {
1455 if (strcasecmp(phy_conn_name, "mii") == 0)
1456 sc->phy_conn_type = PHY_CONN_MII;
1457 else if (strcasecmp(phy_conn_name, "rmii") == 0)
1458 sc->phy_conn_type = PHY_CONN_RMII;
1459 else if (strcasecmp(phy_conn_name, "rgmii") == 0)
1460 sc->phy_conn_type = PHY_CONN_RGMII;
1461 }
1462 if (sc->phy_conn_type == PHY_CONN_UNKNOWN) {
1463 device_printf(sc->dev, "No valid 'phy-mode' "
1464 "property found in FDT data for device.\n");
1465 error = ENOATTR;
1466 goto out;
1467 }
1468
1469 callout_init_mtx(&sc->ffec_callout, &sc->mtx, 0);
1470
1471 /* Allocate bus resources for accessing the hardware. */
1472 rid = 0;
1473 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1474 RF_ACTIVE);
1475 if (sc->mem_res == NULL) {
1476 device_printf(dev, "could not allocate memory resources.\n");
1477 error = ENOMEM;
1478 goto out;
1479 }
1480 rid = 0;
1481 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1482 RF_ACTIVE);
1483 if (sc->irq_res == NULL) {
1484 device_printf(dev, "could not allocate interrupt resources.\n");
1485 error = ENOMEM;
1486 goto out;
1487 }
1488
1489 /*
1490 * Set up TX descriptor ring, descriptors, and dma maps.
1491 */
1492 error = bus_dma_tag_create(
1493 bus_get_dma_tag(dev), /* Parent tag. */
1494 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1495 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1496 BUS_SPACE_MAXADDR, /* highaddr */
1497 NULL, NULL, /* filter, filterarg */
1498 TX_DESC_SIZE, 1, /* maxsize, nsegments */
1499 TX_DESC_SIZE, /* maxsegsize */
1500 0, /* flags */
1501 NULL, NULL, /* lockfunc, lockarg */
1502 &sc->txdesc_tag);
1503 if (error != 0) {
1504 device_printf(sc->dev,
1505 "could not create TX ring DMA tag.\n");
1506 goto out;
1507 }
1508
1509 error = bus_dmamem_alloc(sc->txdesc_tag, (void**)&sc->txdesc_ring,
1510 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->txdesc_map);
1511 if (error != 0) {
1512 device_printf(sc->dev,
1513 "could not allocate TX descriptor ring.\n");
1514 goto out;
1515 }
1516
1517 error = bus_dmamap_load(sc->txdesc_tag, sc->txdesc_map, sc->txdesc_ring,
1518 TX_DESC_SIZE, ffec_get1paddr, &sc->txdesc_ring_paddr, 0);
1519 if (error != 0) {
1520 device_printf(sc->dev,
1521 "could not load TX descriptor ring map.\n");
1522 goto out;
1523 }
1524
1525 error = bus_dma_tag_create(
1526 bus_get_dma_tag(dev), /* Parent tag. */
1527 FEC_TXBUF_ALIGN, 0, /* alignment, boundary */
1528 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1529 BUS_SPACE_MAXADDR, /* highaddr */
1530 NULL, NULL, /* filter, filterarg */
1531 MCLBYTES, 1, /* maxsize, nsegments */
1532 MCLBYTES, /* maxsegsize */
1533 0, /* flags */
1534 NULL, NULL, /* lockfunc, lockarg */
1535 &sc->txbuf_tag);
1536 if (error != 0) {
1537 device_printf(sc->dev,
1538 "could not create TX ring DMA tag.\n");
1539 goto out;
1540 }
1541
1542 for (idx = 0; idx < TX_DESC_COUNT; ++idx) {
1543 error = bus_dmamap_create(sc->txbuf_tag, 0,
1544 &sc->txbuf_map[idx].map);
1545 if (error != 0) {
1546 device_printf(sc->dev,
1547 "could not create TX buffer DMA map.\n");
1548 goto out;
1549 }
1550 ffec_setup_txdesc(sc, idx, 0, 0);
1551 }
1552
1553 /*
1554 * Set up RX descriptor ring, descriptors, dma maps, and mbufs.
1555 */
1556 error = bus_dma_tag_create(
1557 bus_get_dma_tag(dev), /* Parent tag. */
1558 FEC_DESC_RING_ALIGN, 0, /* alignment, boundary */
1559 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1560 BUS_SPACE_MAXADDR, /* highaddr */
1561 NULL, NULL, /* filter, filterarg */
1562 RX_DESC_SIZE, 1, /* maxsize, nsegments */
1563 RX_DESC_SIZE, /* maxsegsize */
1564 0, /* flags */
1565 NULL, NULL, /* lockfunc, lockarg */
1566 &sc->rxdesc_tag);
1567 if (error != 0) {
1568 device_printf(sc->dev,
1569 "could not create RX ring DMA tag.\n");
1570 goto out;
1571 }
1572
1573 error = bus_dmamem_alloc(sc->rxdesc_tag, (void **)&sc->rxdesc_ring,
1574 BUS_DMA_COHERENT | BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->rxdesc_map);
1575 if (error != 0) {
1576 device_printf(sc->dev,
1577 "could not allocate RX descriptor ring.\n");
1578 goto out;
1579 }
1580
1581 error = bus_dmamap_load(sc->rxdesc_tag, sc->rxdesc_map, sc->rxdesc_ring,
1582 RX_DESC_SIZE, ffec_get1paddr, &sc->rxdesc_ring_paddr, 0);
1583 if (error != 0) {
1584 device_printf(sc->dev,
1585 "could not load RX descriptor ring map.\n");
1586 goto out;
1587 }
1588
1589 error = bus_dma_tag_create(
1590 bus_get_dma_tag(dev), /* Parent tag. */
1591 1, 0, /* alignment, boundary */
1592 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1593 BUS_SPACE_MAXADDR, /* highaddr */
1594 NULL, NULL, /* filter, filterarg */
1595 MCLBYTES, 1, /* maxsize, nsegments */
1596 MCLBYTES, /* maxsegsize */
1597 0, /* flags */
1598 NULL, NULL, /* lockfunc, lockarg */
1599 &sc->rxbuf_tag);
1600 if (error != 0) {
1601 device_printf(sc->dev,
1602 "could not create RX buf DMA tag.\n");
1603 goto out;
1604 }
1605
1606 for (idx = 0; idx < RX_DESC_COUNT; ++idx) {
1607 error = bus_dmamap_create(sc->rxbuf_tag, 0,
1608 &sc->rxbuf_map[idx].map);
1609 if (error != 0) {
1610 device_printf(sc->dev,
1611 "could not create RX buffer DMA map.\n");
1612 goto out;
1613 }
1614 if ((m = ffec_alloc_mbufcl(sc)) == NULL) {
1615 device_printf(dev, "Could not alloc mbuf\n");
1616 error = ENOMEM;
1617 goto out;
1618 }
1619 if ((error = ffec_setup_rxbuf(sc, idx, m)) != 0) {
1620 device_printf(sc->dev,
1621 "could not create new RX buffer.\n");
1622 goto out;
1623 }
1624 }
1625
1626 /* Try to get the MAC address from the hardware before resetting it. */
1627 ffec_get_hwaddr(sc, eaddr);
1628
1629 /* Reset the hardware. Disables all interrupts. */
1630 WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);
1631
1632 /* Setup interrupt handler. */
1633 error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE,
1634 NULL, ffec_intr, sc, &sc->intr_cookie);
1635 if (error != 0) {
1636 device_printf(dev, "could not setup interrupt handler.\n");
1637 goto out;
1638 }
1639
1640 /*
1641 * Set up the PHY control register.
1642 *
1643 * Speed formula for ENET is md_clock = mac_clock / ((N + 1) * 2).
1644 * Speed formula for FEC is md_clock = mac_clock / (N * 2)
1645 *
1646 * XXX - Revisit this...
1647 *
1648 * For a Wandboard imx6 (ENET) I was originally using 4, but the uboot
1649 * code uses 10. Both values seem to work, but I suspect many modern
1650 * PHY parts can do mdio at speeds far above the standard 2.5 MHz.
1651 *
1652 * Different imx manuals use confusingly different terminology (things
1653 * like "system clock" and "internal module clock") with examples that
1654 * use frequencies that have nothing to do with ethernet, giving the
1655 * vague impression that maybe the clock in question is the periphclock
1656 * or something. In fact, on an imx53 development board (FEC),
1657 * measuring the mdio clock at the pin on the PHY and playing with
1658 * various divisors showed that the root speed was 66 MHz (clk_ipg_root
1659 * aka periphclock) and 13 was the right divisor.
1660 *
1661 * All in all, it seems likely that 13 is a safe divisor for now,
1662 * because if we really do need to base it on the peripheral clock
1663 * speed, then we need a platform-independant get-clock-freq API.
1664 */
1665 mscr = 13 << FEC_MSCR_MII_SPEED_SHIFT;
1666 if (OF_hasprop(ofw_node, "phy-disable-preamble")) {
1667 mscr |= FEC_MSCR_DIS_PRE;
1668 if (bootverbose)
1669 device_printf(dev, "PHY preamble disabled\n");
1670 }
1671 WR4(sc, FEC_MSCR_REG, mscr);
1672
1673 /* Set up the ethernet interface. */
1674 sc->ifp = ifp = if_alloc(IFT_ETHER);
1675
1676 ifp->if_softc = sc;
1677 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1678 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1679 ifp->if_capabilities = IFCAP_VLAN_MTU;
1680 ifp->if_capenable = ifp->if_capabilities;
1681 ifp->if_start = ffec_txstart;
1682 ifp->if_ioctl = ffec_ioctl;
1683 ifp->if_init = ffec_init;
1684 IFQ_SET_MAXLEN(&ifp->if_snd, TX_DESC_COUNT - 1);
1685 ifp->if_snd.ifq_drv_maxlen = TX_DESC_COUNT - 1;
1686 IFQ_SET_READY(&ifp->if_snd);
1687 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
1688
1689 #if 0 /* XXX The hardware keeps stats we could use for these. */
1690 ifp->if_linkmib = &sc->mibdata;
1691 ifp->if_linkmiblen = sizeof(sc->mibdata);
1692 #endif
1693
1694 /* Set up the miigasket hardware (if any). */
1695 ffec_miigasket_setup(sc);
1696
1697 /* Attach the mii driver. */
1698 error = mii_attach(dev, &sc->miibus, ifp, ffec_media_change,
1699 ffec_media_status, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY,
1700 (sc->fectype & FECTYPE_MVF) ? MIIF_FORCEANEG : 0);
1701 if (error != 0) {
1702 device_printf(dev, "PHY attach failed\n");
1703 goto out;
1704 }
1705 sc->mii_softc = device_get_softc(sc->miibus);
1706
1707 /* All ready to run, attach the ethernet interface. */
1708 ether_ifattach(ifp, eaddr);
1709 sc->is_attached = true;
1710
1711 error = 0;
1712 out:
1713
1714 if (error != 0)
1715 ffec_detach(dev);
1716
1717 return (error);
1718 }
1719
1720 static int
ffec_probe(device_t dev)1721 ffec_probe(device_t dev)
1722 {
1723 uintptr_t fectype;
1724
1725 if (!ofw_bus_status_okay(dev))
1726 return (ENXIO);
1727
1728 fectype = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
1729 if (fectype == FECTYPE_NONE)
1730 return (ENXIO);
1731
1732 device_set_desc(dev, (fectype & FECFLAG_GBE) ?
1733 "Freescale Gigabit Ethernet Controller" :
1734 "Freescale Fast Ethernet Controller");
1735
1736 return (BUS_PROBE_DEFAULT);
1737 }
1738
1739
1740 static device_method_t ffec_methods[] = {
1741 /* Device interface. */
1742 DEVMETHOD(device_probe, ffec_probe),
1743 DEVMETHOD(device_attach, ffec_attach),
1744 DEVMETHOD(device_detach, ffec_detach),
1745
1746 /*
1747 DEVMETHOD(device_shutdown, ffec_shutdown),
1748 DEVMETHOD(device_suspend, ffec_suspend),
1749 DEVMETHOD(device_resume, ffec_resume),
1750 */
1751
1752 /* MII interface. */
1753 DEVMETHOD(miibus_readreg, ffec_miibus_readreg),
1754 DEVMETHOD(miibus_writereg, ffec_miibus_writereg),
1755 DEVMETHOD(miibus_statchg, ffec_miibus_statchg),
1756
1757 DEVMETHOD_END
1758 };
1759
1760 static driver_t ffec_driver = {
1761 "ffec",
1762 ffec_methods,
1763 sizeof(struct ffec_softc)
1764 };
1765
1766 static devclass_t ffec_devclass;
1767
1768 DRIVER_MODULE(ffec, simplebus, ffec_driver, ffec_devclass, 0, 0);
1769 DRIVER_MODULE(miibus, ffec, miibus_driver, miibus_devclass, 0, 0);
1770
1771 MODULE_DEPEND(ffec, ether, 1, 1, 1);
1772 MODULE_DEPEND(ffec, miibus, 1, 1, 1);
1773