1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <dev/drm2/drmP.h>
31 #include <dev/drm2/drm_edid.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
33 #include <dev/iicbus/iic.h>
34 #include <dev/iicbus/iiconf.h>
35 #include <dev/iicbus/iicbus.h>
36 #include "radeon.h"
37 #include "atom.h"
38 #include "iicbus_if.h"
39 #include "iicbb_if.h"
40
41 /**
42 * radeon_ddc_probe
43 *
44 */
radeon_ddc_probe(struct radeon_connector * radeon_connector,bool use_aux)45 bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux)
46 {
47 u8 out = 0x0;
48 u8 buf[8];
49 int ret;
50 struct iic_msg msgs[] = {
51 {
52 .slave = DDC_ADDR << 1,
53 .flags = 0,
54 .len = 1,
55 .buf = &out,
56 },
57 {
58 .slave = DDC_ADDR << 1,
59 .flags = IIC_M_RD,
60 .len = 8,
61 .buf = buf,
62 }
63 };
64
65 /* on hw with routers, select right port */
66 if (radeon_connector->router.ddc_valid)
67 radeon_router_select_ddc_port(radeon_connector);
68
69 if (use_aux) {
70 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
71 ret = iicbus_transfer(dig->dp_i2c_bus->adapter, msgs, 2);
72 } else {
73 ret = iicbus_transfer(radeon_connector->ddc_bus->adapter, msgs, 2);
74 }
75
76 if (ret != 0)
77 /* Couldn't find an accessible DDC on this connector */
78 return false;
79 /* Probe also for valid EDID header
80 * EDID header starts with:
81 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.
82 * Only the first 6 bytes must be valid as
83 * drm_edid_block_valid() can fix the last 2 bytes */
84 if (drm_edid_header_is_valid(buf) < 6) {
85 /* Couldn't find an accessible EDID on this
86 * connector */
87 return false;
88 }
89 return true;
90 }
91
92 /* bit banging i2c */
93
radeon_iicbb_pre_xfer(device_t dev)94 static int radeon_iicbb_pre_xfer(device_t dev)
95 {
96 struct radeon_i2c_chan *i2c = device_get_softc(dev);
97 struct radeon_device *rdev = i2c->dev->dev_private;
98 struct radeon_i2c_bus_rec *rec = &i2c->rec;
99 uint32_t temp;
100
101 /* RV410 appears to have a bug where the hw i2c in reset
102 * holds the i2c port in a bad state - switch hw i2c away before
103 * doing DDC - do this for all r200s/r300s/r400s for safety sake
104 */
105 if (rec->hw_capable) {
106 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) {
107 u32 reg;
108
109 if (rdev->family >= CHIP_RV350)
110 reg = RADEON_GPIO_MONID;
111 else if ((rdev->family == CHIP_R300) ||
112 (rdev->family == CHIP_R350))
113 reg = RADEON_GPIO_DVI_DDC;
114 else
115 reg = RADEON_GPIO_CRT2_DDC;
116
117 sx_xlock(&rdev->dc_hw_i2c_mutex);
118 if (rec->a_clk_reg == reg) {
119 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
120 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
121 } else {
122 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
123 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
124 }
125 sx_xunlock(&rdev->dc_hw_i2c_mutex);
126 }
127 }
128
129 /* switch the pads to ddc mode */
130 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) {
131 temp = RREG32(rec->mask_clk_reg);
132 temp &= ~(1 << 16);
133 WREG32(rec->mask_clk_reg, temp);
134 }
135
136 /* clear the output pin values */
137 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask;
138 WREG32(rec->a_clk_reg, temp);
139
140 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask;
141 WREG32(rec->a_data_reg, temp);
142
143 /* set the pins to input */
144 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
145 WREG32(rec->en_clk_reg, temp);
146
147 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
148 WREG32(rec->en_data_reg, temp);
149
150 /* mask the gpio pins for software use */
151 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask;
152 WREG32(rec->mask_clk_reg, temp);
153 temp = RREG32(rec->mask_clk_reg);
154
155 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask;
156 WREG32(rec->mask_data_reg, temp);
157 temp = RREG32(rec->mask_data_reg);
158
159 return 0;
160 }
161
radeon_iicbb_post_xfer(device_t dev)162 static void radeon_iicbb_post_xfer(device_t dev)
163 {
164 struct radeon_i2c_chan *i2c = device_get_softc(dev);
165 struct radeon_device *rdev = i2c->dev->dev_private;
166 struct radeon_i2c_bus_rec *rec = &i2c->rec;
167 uint32_t temp;
168
169 /* unmask the gpio pins for software use */
170 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask;
171 WREG32(rec->mask_clk_reg, temp);
172 temp = RREG32(rec->mask_clk_reg);
173
174 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask;
175 WREG32(rec->mask_data_reg, temp);
176 temp = RREG32(rec->mask_data_reg);
177 }
178
radeon_iicbb_get_clock(device_t dev)179 static int radeon_iicbb_get_clock(device_t dev)
180 {
181 struct radeon_i2c_chan *i2c = device_get_softc(dev);
182 struct radeon_device *rdev = i2c->dev->dev_private;
183 struct radeon_i2c_bus_rec *rec = &i2c->rec;
184 uint32_t val;
185
186 /* read the value off the pin */
187 val = RREG32(rec->y_clk_reg);
188 val &= rec->y_clk_mask;
189
190 return (val != 0);
191 }
192
193
radeon_iicbb_get_data(device_t dev)194 static int radeon_iicbb_get_data(device_t dev)
195 {
196 struct radeon_i2c_chan *i2c = device_get_softc(dev);
197 struct radeon_device *rdev = i2c->dev->dev_private;
198 struct radeon_i2c_bus_rec *rec = &i2c->rec;
199 uint32_t val;
200
201 /* read the value off the pin */
202 val = RREG32(rec->y_data_reg);
203 val &= rec->y_data_mask;
204
205 return (val != 0);
206 }
207
radeon_iicbb_set_clock(device_t dev,int clock)208 static void radeon_iicbb_set_clock(device_t dev, int clock)
209 {
210 struct radeon_i2c_chan *i2c = device_get_softc(dev);
211 struct radeon_device *rdev = i2c->dev->dev_private;
212 struct radeon_i2c_bus_rec *rec = &i2c->rec;
213 uint32_t val;
214
215 /* set pin direction */
216 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask;
217 val |= clock ? 0 : rec->en_clk_mask;
218 WREG32(rec->en_clk_reg, val);
219 }
220
radeon_iicbb_set_data(device_t dev,int data)221 static void radeon_iicbb_set_data(device_t dev, int data)
222 {
223 struct radeon_i2c_chan *i2c = device_get_softc(dev);
224 struct radeon_device *rdev = i2c->dev->dev_private;
225 struct radeon_i2c_bus_rec *rec = &i2c->rec;
226 uint32_t val;
227
228 /* set pin direction */
229 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask;
230 val |= data ? 0 : rec->en_data_mask;
231 WREG32(rec->en_data_reg, val);
232 }
233
234 static int
radeon_iicbb_probe(device_t dev)235 radeon_iicbb_probe(device_t dev)
236 {
237
238 return (BUS_PROBE_DEFAULT);
239 }
240
241 static int
radeon_iicbb_attach(device_t dev)242 radeon_iicbb_attach(device_t dev)
243 {
244 struct radeon_i2c_chan *i2c;
245 device_t iic_dev;
246
247 i2c = device_get_softc(dev);
248 device_set_desc(dev, i2c->name);
249
250 /* add generic bit-banging code */
251 iic_dev = device_add_child(dev, "iicbb", -1);
252 if (iic_dev == NULL)
253 return (ENXIO);
254 device_quiet(iic_dev);
255
256 /* attach and probe added child */
257 bus_generic_attach(dev);
258
259 return (0);
260 }
261
262 static int
radeon_iicbb_detach(device_t dev)263 radeon_iicbb_detach(device_t dev)
264 {
265
266 /* detach bit-banding code. */
267 bus_generic_detach(dev);
268
269 /* delete bit-banding code. */
270 device_delete_children(dev);
271 return (0);
272 }
273
274 static int
radeon_iicbb_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)275 radeon_iicbb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
276 {
277
278 /* Not sure what to do here. */
279 return 0;
280 }
281
282 static device_method_t radeon_iicbb_methods[] = {
283 DEVMETHOD(device_probe, radeon_iicbb_probe),
284 DEVMETHOD(device_attach, radeon_iicbb_attach),
285 DEVMETHOD(device_detach, radeon_iicbb_detach),
286
287 DEVMETHOD(bus_add_child, bus_generic_add_child),
288 DEVMETHOD(bus_print_child, bus_generic_print_child),
289
290 DEVMETHOD(iicbb_reset, radeon_iicbb_reset),
291 DEVMETHOD(iicbb_pre_xfer, radeon_iicbb_pre_xfer),
292 DEVMETHOD(iicbb_post_xfer, radeon_iicbb_post_xfer),
293 DEVMETHOD(iicbb_setsda, radeon_iicbb_set_data),
294 DEVMETHOD(iicbb_setscl, radeon_iicbb_set_clock),
295 DEVMETHOD(iicbb_getsda, radeon_iicbb_get_data),
296 DEVMETHOD(iicbb_getscl, radeon_iicbb_get_clock),
297 DEVMETHOD_END
298 };
299
300 static driver_t radeon_iicbb_driver = {
301 "radeon_iicbb",
302 radeon_iicbb_methods,
303 0 /* softc will be allocated by parent */
304 };
305 static devclass_t radeon_iicbb_devclass;
306 DRIVER_MODULE_ORDERED(radeon_iicbb, drmn, radeon_iicbb_driver,
307 radeon_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
308 DRIVER_MODULE(iicbb, radeon_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
309
310 /* hw i2c */
311
radeon_get_i2c_prescale(struct radeon_device * rdev)312 static u32 radeon_get_i2c_prescale(struct radeon_device *rdev)
313 {
314 u32 sclk = rdev->pm.current_sclk;
315 u32 prescale = 0;
316 u32 nm;
317 u8 n, m, loop;
318 int i2c_clock;
319
320 switch (rdev->family) {
321 case CHIP_R100:
322 case CHIP_RV100:
323 case CHIP_RS100:
324 case CHIP_RV200:
325 case CHIP_RS200:
326 case CHIP_R200:
327 case CHIP_RV250:
328 case CHIP_RS300:
329 case CHIP_RV280:
330 case CHIP_R300:
331 case CHIP_R350:
332 case CHIP_RV350:
333 i2c_clock = 60;
334 nm = (sclk * 10) / (i2c_clock * 4);
335 for (loop = 1; loop < 255; loop++) {
336 if ((nm / loop) < loop)
337 break;
338 }
339 n = loop - 1;
340 m = loop - 2;
341 prescale = m | (n << 8);
342 break;
343 case CHIP_RV380:
344 case CHIP_RS400:
345 case CHIP_RS480:
346 case CHIP_R420:
347 case CHIP_R423:
348 case CHIP_RV410:
349 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
350 break;
351 case CHIP_RS600:
352 case CHIP_RS690:
353 case CHIP_RS740:
354 /* todo */
355 break;
356 case CHIP_RV515:
357 case CHIP_R520:
358 case CHIP_RV530:
359 case CHIP_RV560:
360 case CHIP_RV570:
361 case CHIP_R580:
362 i2c_clock = 50;
363 if (rdev->family == CHIP_R520)
364 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock));
365 else
366 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128;
367 break;
368 case CHIP_R600:
369 case CHIP_RV610:
370 case CHIP_RV630:
371 case CHIP_RV670:
372 /* todo */
373 break;
374 case CHIP_RV620:
375 case CHIP_RV635:
376 case CHIP_RS780:
377 case CHIP_RS880:
378 case CHIP_RV770:
379 case CHIP_RV730:
380 case CHIP_RV710:
381 case CHIP_RV740:
382 /* todo */
383 break;
384 case CHIP_CEDAR:
385 case CHIP_REDWOOD:
386 case CHIP_JUNIPER:
387 case CHIP_CYPRESS:
388 case CHIP_HEMLOCK:
389 /* todo */
390 break;
391 default:
392 DRM_ERROR("i2c: unhandled radeon chip\n");
393 break;
394 }
395 return prescale;
396 }
397
398
399 /* hw i2c engine for r1xx-4xx hardware
400 * hw can buffer up to 15 bytes
401 */
r100_hw_i2c_xfer(struct radeon_i2c_chan * i2c,struct iic_msg * msgs,int num)402 static int r100_hw_i2c_xfer(struct radeon_i2c_chan *i2c,
403 struct iic_msg *msgs, int num)
404 {
405 struct radeon_device *rdev = i2c->dev->dev_private;
406 struct radeon_i2c_bus_rec *rec = &i2c->rec;
407 struct iic_msg *p;
408 int i, j, k, ret = 0;
409 u32 prescale;
410 u32 i2c_cntl_0, i2c_cntl_1, i2c_data;
411 u32 tmp, reg;
412
413 sx_xlock(&rdev->dc_hw_i2c_mutex);
414 /* take the pm lock since we need a constant sclk */
415 sx_xlock(&rdev->pm.mutex);
416
417 prescale = radeon_get_i2c_prescale(rdev);
418
419 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) |
420 RADEON_I2C_DRIVE_EN |
421 RADEON_I2C_START |
422 RADEON_I2C_STOP |
423 RADEON_I2C_GO);
424
425 if (rdev->is_atom_bios) {
426 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
427 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
428 }
429
430 if (rec->mm_i2c) {
431 i2c_cntl_0 = RADEON_I2C_CNTL_0;
432 i2c_cntl_1 = RADEON_I2C_CNTL_1;
433 i2c_data = RADEON_I2C_DATA;
434 } else {
435 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0;
436 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1;
437 i2c_data = RADEON_DVI_I2C_DATA;
438
439 switch (rdev->family) {
440 case CHIP_R100:
441 case CHIP_RV100:
442 case CHIP_RS100:
443 case CHIP_RV200:
444 case CHIP_RS200:
445 case CHIP_RS300:
446 switch (rec->mask_clk_reg) {
447 case RADEON_GPIO_DVI_DDC:
448 /* no gpio select bit */
449 break;
450 default:
451 DRM_ERROR("gpio not supported with hw i2c\n");
452 ret = -EINVAL;
453 goto done;
454 }
455 break;
456 case CHIP_R200:
457 /* only bit 4 on r200 */
458 switch (rec->mask_clk_reg) {
459 case RADEON_GPIO_DVI_DDC:
460 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
461 break;
462 case RADEON_GPIO_MONID:
463 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
464 break;
465 default:
466 DRM_ERROR("gpio not supported with hw i2c\n");
467 ret = -EINVAL;
468 goto done;
469 }
470 break;
471 case CHIP_RV250:
472 case CHIP_RV280:
473 /* bits 3 and 4 */
474 switch (rec->mask_clk_reg) {
475 case RADEON_GPIO_DVI_DDC:
476 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
477 break;
478 case RADEON_GPIO_VGA_DDC:
479 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
480 break;
481 case RADEON_GPIO_CRT2_DDC:
482 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
483 break;
484 default:
485 DRM_ERROR("gpio not supported with hw i2c\n");
486 ret = -EINVAL;
487 goto done;
488 }
489 break;
490 case CHIP_R300:
491 case CHIP_R350:
492 /* only bit 4 on r300/r350 */
493 switch (rec->mask_clk_reg) {
494 case RADEON_GPIO_VGA_DDC:
495 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
496 break;
497 case RADEON_GPIO_DVI_DDC:
498 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
499 break;
500 default:
501 DRM_ERROR("gpio not supported with hw i2c\n");
502 ret = -EINVAL;
503 goto done;
504 }
505 break;
506 case CHIP_RV350:
507 case CHIP_RV380:
508 case CHIP_R420:
509 case CHIP_R423:
510 case CHIP_RV410:
511 case CHIP_RS400:
512 case CHIP_RS480:
513 /* bits 3 and 4 */
514 switch (rec->mask_clk_reg) {
515 case RADEON_GPIO_VGA_DDC:
516 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1);
517 break;
518 case RADEON_GPIO_DVI_DDC:
519 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2);
520 break;
521 case RADEON_GPIO_MONID:
522 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3);
523 break;
524 default:
525 DRM_ERROR("gpio not supported with hw i2c\n");
526 ret = -EINVAL;
527 goto done;
528 }
529 break;
530 default:
531 DRM_ERROR("unsupported asic\n");
532 ret = -EINVAL;
533 goto done;
534 break;
535 }
536 }
537
538 /* check for bus probe */
539 p = &msgs[0];
540 if ((num == 1) && (p->len == 0)) {
541 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
542 RADEON_I2C_NACK |
543 RADEON_I2C_HALT |
544 RADEON_I2C_SOFT_RST));
545 WREG32(i2c_data, (p->slave << 1) & 0xff);
546 WREG32(i2c_data, 0);
547 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
548 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
549 RADEON_I2C_EN |
550 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
551 WREG32(i2c_cntl_0, reg);
552 for (k = 0; k < 32; k++) {
553 udelay(10);
554 tmp = RREG32(i2c_cntl_0);
555 if (tmp & RADEON_I2C_GO)
556 continue;
557 tmp = RREG32(i2c_cntl_0);
558 if (tmp & RADEON_I2C_DONE)
559 break;
560 else {
561 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
562 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
563 ret = -EIO;
564 goto done;
565 }
566 }
567 goto done;
568 }
569
570 for (i = 0; i < num; i++) {
571 p = &msgs[i];
572 for (j = 0; j < p->len; j++) {
573 if (p->flags & IIC_M_RD) {
574 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
575 RADEON_I2C_NACK |
576 RADEON_I2C_HALT |
577 RADEON_I2C_SOFT_RST));
578 WREG32(i2c_data, ((p->slave << 1) & 0xff) | 0x1);
579 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
580 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
581 RADEON_I2C_EN |
582 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
583 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE);
584 for (k = 0; k < 32; k++) {
585 udelay(10);
586 tmp = RREG32(i2c_cntl_0);
587 if (tmp & RADEON_I2C_GO)
588 continue;
589 tmp = RREG32(i2c_cntl_0);
590 if (tmp & RADEON_I2C_DONE)
591 break;
592 else {
593 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
594 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
595 ret = -EIO;
596 goto done;
597 }
598 }
599 p->buf[j] = RREG32(i2c_data) & 0xff;
600 } else {
601 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
602 RADEON_I2C_NACK |
603 RADEON_I2C_HALT |
604 RADEON_I2C_SOFT_RST));
605 WREG32(i2c_data, (p->slave << 1) & 0xff);
606 WREG32(i2c_data, p->buf[j]);
607 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) |
608 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) |
609 RADEON_I2C_EN |
610 (48 << RADEON_I2C_TIME_LIMIT_SHIFT)));
611 WREG32(i2c_cntl_0, reg);
612 for (k = 0; k < 32; k++) {
613 udelay(10);
614 tmp = RREG32(i2c_cntl_0);
615 if (tmp & RADEON_I2C_GO)
616 continue;
617 tmp = RREG32(i2c_cntl_0);
618 if (tmp & RADEON_I2C_DONE)
619 break;
620 else {
621 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
622 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT);
623 ret = -EIO;
624 goto done;
625 }
626 }
627 }
628 }
629 }
630
631 done:
632 WREG32(i2c_cntl_0, 0);
633 WREG32(i2c_cntl_1, 0);
634 WREG32(i2c_cntl_0, (RADEON_I2C_DONE |
635 RADEON_I2C_NACK |
636 RADEON_I2C_HALT |
637 RADEON_I2C_SOFT_RST));
638
639 if (rdev->is_atom_bios) {
640 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
641 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
642 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
643 }
644
645 sx_xunlock(&rdev->pm.mutex);
646 sx_xunlock(&rdev->dc_hw_i2c_mutex);
647
648 return ret;
649 }
650
651 /* hw i2c engine for r5xx hardware
652 * hw can buffer up to 15 bytes
653 */
r500_hw_i2c_xfer(struct radeon_i2c_chan * i2c,struct iic_msg * msgs,int num)654 static int r500_hw_i2c_xfer(struct radeon_i2c_chan *i2c,
655 struct iic_msg *msgs, int num)
656 {
657 struct radeon_device *rdev = i2c->dev->dev_private;
658 struct radeon_i2c_bus_rec *rec = &i2c->rec;
659 struct iic_msg *p;
660 int i, j, remaining, current_count, buffer_offset, ret = 0;
661 u32 prescale;
662 u32 tmp, reg;
663 u32 saved1, saved2;
664
665 sx_xlock(&rdev->dc_hw_i2c_mutex);
666 /* take the pm lock since we need a constant sclk */
667 sx_xlock(&rdev->pm.mutex);
668
669 prescale = radeon_get_i2c_prescale(rdev);
670
671 /* clear gpio mask bits */
672 tmp = RREG32(rec->mask_clk_reg);
673 tmp &= ~rec->mask_clk_mask;
674 WREG32(rec->mask_clk_reg, tmp);
675 tmp = RREG32(rec->mask_clk_reg);
676
677 tmp = RREG32(rec->mask_data_reg);
678 tmp &= ~rec->mask_data_mask;
679 WREG32(rec->mask_data_reg, tmp);
680 tmp = RREG32(rec->mask_data_reg);
681
682 /* clear pin values */
683 tmp = RREG32(rec->a_clk_reg);
684 tmp &= ~rec->a_clk_mask;
685 WREG32(rec->a_clk_reg, tmp);
686 tmp = RREG32(rec->a_clk_reg);
687
688 tmp = RREG32(rec->a_data_reg);
689 tmp &= ~rec->a_data_mask;
690 WREG32(rec->a_data_reg, tmp);
691 tmp = RREG32(rec->a_data_reg);
692
693 /* set the pins to input */
694 tmp = RREG32(rec->en_clk_reg);
695 tmp &= ~rec->en_clk_mask;
696 WREG32(rec->en_clk_reg, tmp);
697 tmp = RREG32(rec->en_clk_reg);
698
699 tmp = RREG32(rec->en_data_reg);
700 tmp &= ~rec->en_data_mask;
701 WREG32(rec->en_data_reg, tmp);
702 tmp = RREG32(rec->en_data_reg);
703
704 /* */
705 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
706 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE);
707 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1);
708 saved2 = RREG32(0x494);
709 WREG32(0x494, saved2 | 0x1);
710
711 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C);
712 for (i = 0; i < 50; i++) {
713 udelay(1);
714 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C)
715 break;
716 }
717 if (i == 50) {
718 DRM_ERROR("failed to get i2c bus\n");
719 ret = -EBUSY;
720 goto done;
721 }
722
723 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN;
724 switch (rec->mask_clk_reg) {
725 case AVIVO_DC_GPIO_DDC1_MASK:
726 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1);
727 break;
728 case AVIVO_DC_GPIO_DDC2_MASK:
729 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2);
730 break;
731 case AVIVO_DC_GPIO_DDC3_MASK:
732 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3);
733 break;
734 default:
735 DRM_ERROR("gpio not supported with hw i2c\n");
736 ret = -EINVAL;
737 goto done;
738 }
739
740 /* check for bus probe */
741 p = &msgs[0];
742 if ((num == 1) && (p->len == 0)) {
743 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
744 AVIVO_DC_I2C_NACK |
745 AVIVO_DC_I2C_HALT));
746 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
747 udelay(1);
748 WREG32(AVIVO_DC_I2C_RESET, 0);
749
750 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff);
751 WREG32(AVIVO_DC_I2C_DATA, 0);
752
753 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
754 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
755 AVIVO_DC_I2C_DATA_COUNT(1) |
756 (prescale << 16)));
757 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
758 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
759 for (j = 0; j < 200; j++) {
760 udelay(50);
761 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
762 if (tmp & AVIVO_DC_I2C_GO)
763 continue;
764 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
765 if (tmp & AVIVO_DC_I2C_DONE)
766 break;
767 else {
768 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
769 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
770 ret = -EIO;
771 goto done;
772 }
773 }
774 goto done;
775 }
776
777 for (i = 0; i < num; i++) {
778 p = &msgs[i];
779 remaining = p->len;
780 buffer_offset = 0;
781 if (p->flags & IIC_M_RD) {
782 while (remaining) {
783 if (remaining > 15)
784 current_count = 15;
785 else
786 current_count = remaining;
787 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
788 AVIVO_DC_I2C_NACK |
789 AVIVO_DC_I2C_HALT));
790 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
791 udelay(1);
792 WREG32(AVIVO_DC_I2C_RESET, 0);
793
794 WREG32(AVIVO_DC_I2C_DATA, ((p->slave << 1) & 0xff) | 0x1);
795 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
796 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
797 AVIVO_DC_I2C_DATA_COUNT(current_count) |
798 (prescale << 16)));
799 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE);
800 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
801 for (j = 0; j < 200; j++) {
802 udelay(50);
803 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
804 if (tmp & AVIVO_DC_I2C_GO)
805 continue;
806 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
807 if (tmp & AVIVO_DC_I2C_DONE)
808 break;
809 else {
810 DRM_DEBUG("i2c read error 0x%08x\n", tmp);
811 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
812 ret = -EIO;
813 goto done;
814 }
815 }
816 for (j = 0; j < current_count; j++)
817 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff;
818 remaining -= current_count;
819 buffer_offset += current_count;
820 }
821 } else {
822 while (remaining) {
823 if (remaining > 15)
824 current_count = 15;
825 else
826 current_count = remaining;
827 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
828 AVIVO_DC_I2C_NACK |
829 AVIVO_DC_I2C_HALT));
830 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
831 udelay(1);
832 WREG32(AVIVO_DC_I2C_RESET, 0);
833
834 WREG32(AVIVO_DC_I2C_DATA, (p->slave << 1) & 0xff);
835 for (j = 0; j < current_count; j++)
836 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]);
837
838 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48));
839 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) |
840 AVIVO_DC_I2C_DATA_COUNT(current_count) |
841 (prescale << 16)));
842 WREG32(AVIVO_DC_I2C_CONTROL1, reg);
843 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO);
844 for (j = 0; j < 200; j++) {
845 udelay(50);
846 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
847 if (tmp & AVIVO_DC_I2C_GO)
848 continue;
849 tmp = RREG32(AVIVO_DC_I2C_STATUS1);
850 if (tmp & AVIVO_DC_I2C_DONE)
851 break;
852 else {
853 DRM_DEBUG("i2c write error 0x%08x\n", tmp);
854 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT);
855 ret = -EIO;
856 goto done;
857 }
858 }
859 remaining -= current_count;
860 buffer_offset += current_count;
861 }
862 }
863 }
864
865 done:
866 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE |
867 AVIVO_DC_I2C_NACK |
868 AVIVO_DC_I2C_HALT));
869 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET);
870 udelay(1);
871 WREG32(AVIVO_DC_I2C_RESET, 0);
872
873 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C);
874 WREG32(AVIVO_DC_I2C_CONTROL1, saved1);
875 WREG32(0x494, saved2);
876 tmp = RREG32(RADEON_BIOS_6_SCRATCH);
877 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE;
878 WREG32(RADEON_BIOS_6_SCRATCH, tmp);
879
880 sx_xunlock(&rdev->pm.mutex);
881 sx_xunlock(&rdev->dc_hw_i2c_mutex);
882
883 return ret;
884 }
885
radeon_hw_i2c_xfer(device_t dev,struct iic_msg * msgs,uint32_t num)886 static int radeon_hw_i2c_xfer(device_t dev,
887 struct iic_msg *msgs, uint32_t num)
888 {
889 struct radeon_i2c_chan *i2c = device_get_softc(dev);
890 struct radeon_device *rdev = i2c->dev->dev_private;
891 struct radeon_i2c_bus_rec *rec = &i2c->rec;
892 int ret = 0;
893
894 switch (rdev->family) {
895 case CHIP_R100:
896 case CHIP_RV100:
897 case CHIP_RS100:
898 case CHIP_RV200:
899 case CHIP_RS200:
900 case CHIP_R200:
901 case CHIP_RV250:
902 case CHIP_RS300:
903 case CHIP_RV280:
904 case CHIP_R300:
905 case CHIP_R350:
906 case CHIP_RV350:
907 case CHIP_RV380:
908 case CHIP_R420:
909 case CHIP_R423:
910 case CHIP_RV410:
911 case CHIP_RS400:
912 case CHIP_RS480:
913 ret = r100_hw_i2c_xfer(i2c, msgs, num);
914 break;
915 case CHIP_RS600:
916 case CHIP_RS690:
917 case CHIP_RS740:
918 /* XXX fill in hw i2c implementation */
919 break;
920 case CHIP_RV515:
921 case CHIP_R520:
922 case CHIP_RV530:
923 case CHIP_RV560:
924 case CHIP_RV570:
925 case CHIP_R580:
926 if (rec->mm_i2c)
927 ret = r100_hw_i2c_xfer(i2c, msgs, num);
928 else
929 ret = r500_hw_i2c_xfer(i2c, msgs, num);
930 break;
931 case CHIP_R600:
932 case CHIP_RV610:
933 case CHIP_RV630:
934 case CHIP_RV670:
935 /* XXX fill in hw i2c implementation */
936 break;
937 case CHIP_RV620:
938 case CHIP_RV635:
939 case CHIP_RS780:
940 case CHIP_RS880:
941 case CHIP_RV770:
942 case CHIP_RV730:
943 case CHIP_RV710:
944 case CHIP_RV740:
945 /* XXX fill in hw i2c implementation */
946 break;
947 case CHIP_CEDAR:
948 case CHIP_REDWOOD:
949 case CHIP_JUNIPER:
950 case CHIP_CYPRESS:
951 case CHIP_HEMLOCK:
952 /* XXX fill in hw i2c implementation */
953 break;
954 default:
955 DRM_ERROR("i2c: unhandled radeon chip\n");
956 ret = -EIO;
957 break;
958 }
959
960 return -ret;
961 }
962
963 static int
radeon_hw_i2c_probe(device_t dev)964 radeon_hw_i2c_probe(device_t dev)
965 {
966
967 return (BUS_PROBE_SPECIFIC);
968 }
969
970 static int
radeon_hw_i2c_attach(device_t dev)971 radeon_hw_i2c_attach(device_t dev)
972 {
973 struct radeon_i2c_chan *i2c;
974 device_t iic_dev;
975
976 i2c = device_get_softc(dev);
977 device_set_desc(dev, i2c->name);
978
979 /* add generic bit-banging code */
980 iic_dev = device_add_child(dev, "iicbus", -1);
981 if (iic_dev == NULL)
982 return (ENXIO);
983 device_quiet(iic_dev);
984
985 /* attach and probe added child */
986 bus_generic_attach(dev);
987
988 return (0);
989 }
990
991 static int
radeon_hw_i2c_detach(device_t dev)992 radeon_hw_i2c_detach(device_t dev)
993 {
994
995 /* detach bit-banding code. */
996 bus_generic_detach(dev);
997
998 /* delete bit-banding code. */
999 device_delete_children(dev);
1000 return (0);
1001 }
1002
1003 static int
radeon_hw_i2c_reset(device_t dev,u_char speed,u_char addr,u_char * oldaddr)1004 radeon_hw_i2c_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
1005 {
1006
1007 /* Not sure what to do here. */
1008 return 0;
1009 }
1010
1011
1012 static device_method_t radeon_hw_i2c_methods[] = {
1013 DEVMETHOD(device_probe, radeon_hw_i2c_probe),
1014 DEVMETHOD(device_attach, radeon_hw_i2c_attach),
1015 DEVMETHOD(device_detach, radeon_hw_i2c_detach),
1016 DEVMETHOD(iicbus_reset, radeon_hw_i2c_reset),
1017 DEVMETHOD(iicbus_transfer, radeon_hw_i2c_xfer),
1018 DEVMETHOD_END
1019 };
1020
1021 static driver_t radeon_hw_i2c_driver = {
1022 "radeon_hw_i2c",
1023 radeon_hw_i2c_methods,
1024 0 /* softc will be allocated by parent */
1025 };
1026
1027 static devclass_t radeon_hw_i2c_devclass;
1028 DRIVER_MODULE_ORDERED(radeon_hw_i2c, drm, radeon_hw_i2c_driver,
1029 radeon_hw_i2c_devclass, 0, 0, SI_ORDER_FIRST);
1030 DRIVER_MODULE(iicbus, radeon_hw_i2c, iicbus_driver, iicbus_devclass, 0, 0);
1031
radeon_i2c_create(struct drm_device * dev,struct radeon_i2c_bus_rec * rec,const char * name)1032 struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
1033 struct radeon_i2c_bus_rec *rec,
1034 const char *name)
1035 {
1036 struct radeon_device *rdev = dev->dev_private;
1037 struct radeon_i2c_chan *i2c;
1038 device_t iicbus_dev;
1039 int ret;
1040
1041 /* don't add the mm_i2c bus unless hw_i2c is enabled */
1042 if (rec->mm_i2c && (radeon_hw_i2c == 0))
1043 return NULL;
1044
1045 i2c = malloc(sizeof(struct radeon_i2c_chan),
1046 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1047 if (i2c == NULL)
1048 return NULL;
1049
1050 /*
1051 * Grab Giant before messing with newbus devices, just in case
1052 * we do not hold it already.
1053 */
1054 mtx_lock(&Giant);
1055
1056 i2c->rec = *rec;
1057 i2c->dev = dev;
1058 if (rec->mm_i2c ||
1059 (rec->hw_capable &&
1060 radeon_hw_i2c &&
1061 ((rdev->family <= CHIP_RS480) ||
1062 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) {
1063 /* set the radeon hw i2c adapter */
1064 snprintf(i2c->name, sizeof(i2c->name),
1065 "Radeon i2c hw bus %s", name);
1066 iicbus_dev = device_add_child(dev->dev, "radeon_hw_i2c", -1);
1067 if (iicbus_dev == NULL) {
1068 DRM_ERROR("Failed to create bridge for hw i2c %s\n",
1069 name);
1070 goto out_free;
1071 }
1072 device_quiet(iicbus_dev);
1073 device_set_softc(iicbus_dev, i2c);
1074
1075 ret = device_probe_and_attach(iicbus_dev);
1076 if (ret != 0) {
1077 DRM_ERROR("Attach failed for bridge for hw i2c %s\n",
1078 name);
1079 device_delete_child(dev->dev, iicbus_dev);
1080 goto out_free;
1081 }
1082
1083 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1);
1084 if (i2c->adapter == NULL) {
1085 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n");
1086 device_delete_child(dev->dev, iicbus_dev);
1087 goto out_free;
1088 }
1089 } else if (rec->hw_capable &&
1090 radeon_hw_i2c &&
1091 ASIC_IS_DCE3(rdev)) {
1092 /* hw i2c using atom */
1093 snprintf(i2c->name, sizeof(i2c->name),
1094 "Radeon i2c hw bus %s", name);
1095 iicbus_dev = device_add_child(dev->dev, "radeon_atom_hw_i2c", -1);
1096 if (iicbus_dev == NULL) {
1097 DRM_ERROR("Failed to create bridge for hw i2c %s\n",
1098 name);
1099 goto out_free;
1100 }
1101 device_quiet(iicbus_dev);
1102 device_set_softc(iicbus_dev, i2c);
1103
1104 ret = device_probe_and_attach(iicbus_dev);
1105 if (ret != 0) {
1106 DRM_ERROR("Attach failed for bridge for hw i2c %s\n",
1107 name);
1108 device_delete_child(dev->dev, iicbus_dev);
1109 goto out_free;
1110 }
1111
1112 i2c->adapter = device_find_child(iicbus_dev, "iicbus", -1);
1113 if (i2c->adapter == NULL) {
1114 DRM_ERROR("hw i2c bridge doesn't have iicbus child\n");
1115 device_delete_child(dev->dev, iicbus_dev);
1116 goto out_free;
1117 }
1118 } else {
1119 device_t iicbb_dev;
1120
1121 /* set the radeon bit adapter */
1122 snprintf(i2c->name, sizeof(i2c->name),
1123 "Radeon i2c bit bus %s", name);
1124 iicbus_dev = device_add_child(dev->dev, "radeon_iicbb", -1);
1125 if (iicbus_dev == NULL) {
1126 DRM_ERROR("Failed to create bridge for bb i2c %s\n",
1127 name);
1128 goto out_free;
1129 }
1130 device_quiet(iicbus_dev);
1131 device_set_softc(iicbus_dev, i2c);
1132
1133 ret = device_probe_and_attach(iicbus_dev);
1134 if (ret != 0) {
1135 DRM_ERROR("Attach failed for bridge for bb i2c %s\n",
1136 name);
1137 device_delete_child(dev->dev, iicbus_dev);
1138 goto out_free;
1139 }
1140
1141 iicbb_dev = device_find_child(iicbus_dev, "iicbb", -1);
1142 if (iicbb_dev == NULL) {
1143 DRM_ERROR("bb i2c bridge doesn't have iicbb child\n");
1144 device_delete_child(dev->dev, iicbus_dev);
1145 goto out_free;
1146 }
1147
1148 i2c->adapter = device_find_child(iicbb_dev, "iicbus", -1);
1149 if (i2c->adapter == NULL) {
1150 DRM_ERROR(
1151 "bbbus bridge doesn't have iicbus grandchild\n");
1152 device_delete_child(dev->dev, iicbus_dev);
1153 goto out_free;
1154 }
1155 }
1156
1157 i2c->iic_bus = iicbus_dev;
1158
1159 mtx_unlock(&Giant);
1160
1161 return i2c;
1162 out_free:
1163 mtx_unlock(&Giant);
1164 free(i2c, DRM_MEM_DRIVER);
1165 return NULL;
1166
1167 }
1168
radeon_i2c_create_dp(struct drm_device * dev,struct radeon_i2c_bus_rec * rec,const char * name)1169 struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
1170 struct radeon_i2c_bus_rec *rec,
1171 const char *name)
1172 {
1173 struct radeon_i2c_chan *i2c;
1174 int ret;
1175
1176 i2c = malloc(sizeof(struct radeon_i2c_chan),
1177 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
1178 if (i2c == NULL)
1179 return NULL;
1180
1181 i2c->rec = *rec;
1182 i2c->dev = dev;
1183 snprintf(i2c->name, sizeof(i2c->name),
1184 "Radeon aux bus %s", name);
1185 ret = iic_dp_aux_add_bus(dev->dev, i2c->name,
1186 radeon_dp_i2c_aux_ch, i2c, &i2c->iic_bus,
1187 &i2c->adapter);
1188 if (ret) {
1189 DRM_INFO("Failed to register i2c %s\n", name);
1190 goto out_free;
1191 }
1192
1193 return i2c;
1194 out_free:
1195 free(i2c, DRM_MEM_DRIVER);
1196 return NULL;
1197
1198 }
1199
radeon_i2c_destroy(struct radeon_i2c_chan * i2c)1200 void radeon_i2c_destroy(struct radeon_i2c_chan *i2c)
1201 {
1202 if (!i2c)
1203 return;
1204 if (i2c->iic_bus != NULL) {
1205 int ret;
1206
1207 mtx_lock(&Giant);
1208 ret = device_delete_child(i2c->dev->dev, i2c->iic_bus);
1209 mtx_unlock(&Giant);
1210 KASSERT(ret == 0, ("unable to detach iic bus %s: %d",
1211 i2c->name, ret));
1212 }
1213 free(i2c, DRM_MEM_DRIVER);
1214 }
1215
1216 /* Add the default buses */
radeon_i2c_init(struct radeon_device * rdev)1217 void radeon_i2c_init(struct radeon_device *rdev)
1218 {
1219 if (rdev->is_atom_bios)
1220 radeon_atombios_i2c_init(rdev);
1221 else
1222 radeon_combios_i2c_init(rdev);
1223 }
1224
1225 /* remove all the buses */
radeon_i2c_fini(struct radeon_device * rdev)1226 void radeon_i2c_fini(struct radeon_device *rdev)
1227 {
1228 int i;
1229
1230 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1231 if (rdev->i2c_bus[i]) {
1232 radeon_i2c_destroy(rdev->i2c_bus[i]);
1233 rdev->i2c_bus[i] = NULL;
1234 }
1235 }
1236 }
1237
1238 /* Add additional buses */
radeon_i2c_add(struct radeon_device * rdev,struct radeon_i2c_bus_rec * rec,const char * name)1239 void radeon_i2c_add(struct radeon_device *rdev,
1240 struct radeon_i2c_bus_rec *rec,
1241 const char *name)
1242 {
1243 struct drm_device *dev = rdev->ddev;
1244 int i;
1245
1246 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1247 if (!rdev->i2c_bus[i]) {
1248 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name);
1249 return;
1250 }
1251 }
1252 }
1253
1254 /* looks up bus based on id */
radeon_i2c_lookup(struct radeon_device * rdev,struct radeon_i2c_bus_rec * i2c_bus)1255 struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
1256 struct radeon_i2c_bus_rec *i2c_bus)
1257 {
1258 int i;
1259
1260 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) {
1261 if (rdev->i2c_bus[i] &&
1262 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) {
1263 return rdev->i2c_bus[i];
1264 }
1265 }
1266 return NULL;
1267 }
1268
radeon_best_encoder(struct drm_connector * connector)1269 struct drm_encoder *radeon_best_encoder(struct drm_connector *connector)
1270 {
1271 return NULL;
1272 }
1273
radeon_i2c_get_byte(struct radeon_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 * val)1274 void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
1275 u8 slave_addr,
1276 u8 addr,
1277 u8 *val)
1278 {
1279 u8 out_buf[2];
1280 u8 in_buf[2];
1281 struct iic_msg msgs[] = {
1282 {
1283 .slave = slave_addr << 1,
1284 .flags = 0,
1285 .len = 1,
1286 .buf = out_buf,
1287 },
1288 {
1289 .slave = slave_addr << 1,
1290 .flags = IIC_M_RD,
1291 .len = 1,
1292 .buf = in_buf,
1293 }
1294 };
1295
1296 out_buf[0] = addr;
1297 out_buf[1] = 0;
1298
1299 if (iicbus_transfer(i2c_bus->adapter, msgs, 2) == 0) {
1300 *val = in_buf[0];
1301 DRM_DEBUG("val = 0x%02x\n", *val);
1302 } else {
1303 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n",
1304 addr, *val);
1305 }
1306 }
1307
radeon_i2c_put_byte(struct radeon_i2c_chan * i2c_bus,u8 slave_addr,u8 addr,u8 val)1308 void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus,
1309 u8 slave_addr,
1310 u8 addr,
1311 u8 val)
1312 {
1313 uint8_t out_buf[2];
1314 struct iic_msg msg = {
1315 .slave = slave_addr << 1,
1316 .flags = 0,
1317 .len = 2,
1318 .buf = out_buf,
1319 };
1320
1321 out_buf[0] = addr;
1322 out_buf[1] = val;
1323
1324 if (iicbus_transfer(i2c_bus->adapter, &msg, 1) != 0)
1325 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n",
1326 addr, val);
1327 }
1328
1329 /* ddc router switching */
radeon_router_select_ddc_port(struct radeon_connector * radeon_connector)1330 void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
1331 {
1332 u8 val;
1333
1334 if (!radeon_connector->router.ddc_valid)
1335 return;
1336
1337 if (!radeon_connector->router_bus)
1338 return;
1339
1340 radeon_i2c_get_byte(radeon_connector->router_bus,
1341 radeon_connector->router.i2c_addr,
1342 0x3, &val);
1343 val &= ~radeon_connector->router.ddc_mux_control_pin;
1344 radeon_i2c_put_byte(radeon_connector->router_bus,
1345 radeon_connector->router.i2c_addr,
1346 0x3, val);
1347 radeon_i2c_get_byte(radeon_connector->router_bus,
1348 radeon_connector->router.i2c_addr,
1349 0x1, &val);
1350 val &= ~radeon_connector->router.ddc_mux_control_pin;
1351 val |= radeon_connector->router.ddc_mux_state;
1352 radeon_i2c_put_byte(radeon_connector->router_bus,
1353 radeon_connector->router.i2c_addr,
1354 0x1, val);
1355 }
1356
1357 /* clock/data router switching */
radeon_router_select_cd_port(struct radeon_connector * radeon_connector)1358 void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
1359 {
1360 u8 val;
1361
1362 if (!radeon_connector->router.cd_valid)
1363 return;
1364
1365 if (!radeon_connector->router_bus)
1366 return;
1367
1368 radeon_i2c_get_byte(radeon_connector->router_bus,
1369 radeon_connector->router.i2c_addr,
1370 0x3, &val);
1371 val &= ~radeon_connector->router.cd_mux_control_pin;
1372 radeon_i2c_put_byte(radeon_connector->router_bus,
1373 radeon_connector->router.i2c_addr,
1374 0x3, val);
1375 radeon_i2c_get_byte(radeon_connector->router_bus,
1376 radeon_connector->router.i2c_addr,
1377 0x1, &val);
1378 val &= ~radeon_connector->router.cd_mux_control_pin;
1379 val |= radeon_connector->router.cd_mux_state;
1380 radeon_i2c_put_byte(radeon_connector->router_bus,
1381 radeon_connector->router.i2c_addr,
1382 0x1, val);
1383 }
1384
1385