1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Christian König
25 * Rafał Miłecki
26 */
27
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
30
31 #include <dev/drm2/drmP.h>
32 #include <dev/drm2/radeon/radeon_drm.h>
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "evergreend.h"
36 #include "atom.h"
37
38 /*
39 * update the N and CTS parameters for a given pixel clock rate
40 */
evergreen_hdmi_update_ACR(struct drm_encoder * encoder,uint32_t clock)41 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
42 {
43 struct drm_device *dev = encoder->dev;
44 struct radeon_device *rdev = dev->dev_private;
45 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
46 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
47 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
48 uint32_t offset = dig->afmt->offset;
49
50 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
51 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
52
53 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
54 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
55
56 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
57 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
58 }
59
60 /*
61 * calculate the crc for a given info frame
62 */
evergreen_hdmi_infoframe_checksum(uint8_t packetType,uint8_t versionNumber,uint8_t length,uint8_t * frame)63 static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
64 uint8_t versionNumber,
65 uint8_t length,
66 uint8_t *frame)
67 {
68 int i;
69 frame[0] = packetType + versionNumber + length;
70 for (i = 1; i <= length; i++)
71 frame[0] += frame[i];
72 frame[0] = 0x100 - frame[0];
73 }
74
75 /*
76 * build a HDMI Video Info Frame
77 */
evergreen_hdmi_videoinfoframe(struct drm_encoder * encoder,uint8_t color_format,int active_information_present,uint8_t active_format_aspect_ratio,uint8_t scan_information,uint8_t colorimetry,uint8_t ex_colorimetry,uint8_t quantization,int ITC,uint8_t picture_aspect_ratio,uint8_t video_format_identification,uint8_t pixel_repetition,uint8_t non_uniform_picture_scaling,uint8_t bar_info_data_valid,uint16_t top_bar,uint16_t bottom_bar,uint16_t left_bar,uint16_t right_bar)78 static void evergreen_hdmi_videoinfoframe(
79 struct drm_encoder *encoder,
80 uint8_t color_format,
81 int active_information_present,
82 uint8_t active_format_aspect_ratio,
83 uint8_t scan_information,
84 uint8_t colorimetry,
85 uint8_t ex_colorimetry,
86 uint8_t quantization,
87 int ITC,
88 uint8_t picture_aspect_ratio,
89 uint8_t video_format_identification,
90 uint8_t pixel_repetition,
91 uint8_t non_uniform_picture_scaling,
92 uint8_t bar_info_data_valid,
93 uint16_t top_bar,
94 uint16_t bottom_bar,
95 uint16_t left_bar,
96 uint16_t right_bar
97 )
98 {
99 struct drm_device *dev = encoder->dev;
100 struct radeon_device *rdev = dev->dev_private;
101 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
102 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
103 uint32_t offset = dig->afmt->offset;
104
105 uint8_t frame[14];
106
107 frame[0x0] = 0;
108 frame[0x1] =
109 (scan_information & 0x3) |
110 ((bar_info_data_valid & 0x3) << 2) |
111 ((active_information_present & 0x1) << 4) |
112 ((color_format & 0x3) << 5);
113 frame[0x2] =
114 (active_format_aspect_ratio & 0xF) |
115 ((picture_aspect_ratio & 0x3) << 4) |
116 ((colorimetry & 0x3) << 6);
117 frame[0x3] =
118 (non_uniform_picture_scaling & 0x3) |
119 ((quantization & 0x3) << 2) |
120 ((ex_colorimetry & 0x7) << 4) |
121 ((ITC & 0x1) << 7);
122 frame[0x4] = (video_format_identification & 0x7F);
123 frame[0x5] = (pixel_repetition & 0xF);
124 frame[0x6] = (top_bar & 0xFF);
125 frame[0x7] = (top_bar >> 8);
126 frame[0x8] = (bottom_bar & 0xFF);
127 frame[0x9] = (bottom_bar >> 8);
128 frame[0xA] = (left_bar & 0xFF);
129 frame[0xB] = (left_bar >> 8);
130 frame[0xC] = (right_bar & 0xFF);
131 frame[0xD] = (right_bar >> 8);
132
133 evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
134 /* Our header values (type, version, length) should be alright, Intel
135 * is using the same. Checksum function also seems to be OK, it works
136 * fine for audio infoframe. However calculated value is always lower
137 * by 2 in comparison to fglrx. It breaks displaying anything in case
138 * of TVs that strictly check the checksum. Hack it manually here to
139 * workaround this issue. */
140 frame[0x0] += 2;
141
142 WREG32(AFMT_AVI_INFO0 + offset,
143 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
144 WREG32(AFMT_AVI_INFO1 + offset,
145 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
146 WREG32(AFMT_AVI_INFO2 + offset,
147 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
148 WREG32(AFMT_AVI_INFO3 + offset,
149 frame[0xC] | (frame[0xD] << 8));
150 }
151
152 /*
153 * update the info frames with the data from the current display mode
154 */
evergreen_hdmi_setmode(struct drm_encoder * encoder,struct drm_display_mode * mode)155 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
156 {
157 struct drm_device *dev = encoder->dev;
158 struct radeon_device *rdev = dev->dev_private;
159 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
160 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
161 uint32_t offset;
162
163 /* Silent, r600_hdmi_enable will raise WARN for us */
164 if (!dig->afmt->enabled)
165 return;
166 offset = dig->afmt->offset;
167
168 r600_audio_set_clock(encoder, mode->clock);
169
170 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
171 HDMI_NULL_SEND); /* send null packets when required */
172
173 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
174
175 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
176 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
177 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
178
179 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
180 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
181 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
182
183 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
184 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
185 HDMI_ACR_SOURCE); /* select SW CTS value */
186
187 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
188 HDMI_NULL_SEND | /* send null packets when required */
189 HDMI_GC_SEND | /* send general control packets */
190 HDMI_GC_CONT); /* send general control packets every frame */
191
192 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
193 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
194 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
195 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
196 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
197
198 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
199 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
200
201 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
202 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
203 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
204
205 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
206
207 evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
208 0, 0, 0, 0, 0, 0);
209
210 evergreen_hdmi_update_ACR(encoder, mode->clock);
211
212 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
213 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
214 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
215 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
216 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
217 }
218