1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 static int ata_sis_chipinit(device_t dev);
55 static int ata_sis_ch_attach(device_t dev);
56 static void ata_sis_reset(device_t dev);
57 static int ata_sis_setmode(device_t dev, int target, int mode);
58
59 /* misc defines */
60 #define SIS_33 1
61 #define SIS_66 2
62 #define SIS_100NEW 3
63 #define SIS_100OLD 4
64 #define SIS_133NEW 5
65 #define SIS_133OLD 6
66 #define SIS_SATA 7
67
68 /*
69 * Silicon Integrated Systems Corp. (SiS) chipset support functions
70 */
71 static int
ata_sis_probe(device_t dev)72 ata_sis_probe(device_t dev)
73 {
74 struct ata_pci_controller *ctlr = device_get_softc(dev);
75 const struct ata_chip_id *idx;
76 static const struct ata_chip_id ids[] =
77 {{ ATA_SIS182, 0x00, SIS_SATA, 0, ATA_SA150, "182" }, /* south */
78 { ATA_SIS181, 0x00, SIS_SATA, 0, ATA_SA150, "181" }, /* south */
79 { ATA_SIS180, 0x00, SIS_SATA, 0, ATA_SA150, "180" }, /* south */
80 { ATA_SIS965, 0x00, SIS_133NEW, 0, ATA_UDMA6, "965" }, /* south */
81 { ATA_SIS964, 0x00, SIS_133NEW, 0, ATA_UDMA6, "964" }, /* south */
82 { ATA_SIS963, 0x00, SIS_133NEW, 0, ATA_UDMA6, "963" }, /* south */
83 { ATA_SIS962, 0x00, SIS_133NEW, 0, ATA_UDMA6, "962" }, /* south */
84
85 { ATA_SIS745, 0x00, SIS_100NEW, 0, ATA_UDMA5, "745" }, /* 1chip */
86 { ATA_SIS735, 0x00, SIS_100NEW, 0, ATA_UDMA5, "735" }, /* 1chip */
87 { ATA_SIS733, 0x00, SIS_100NEW, 0, ATA_UDMA5, "733" }, /* 1chip */
88 { ATA_SIS730, 0x00, SIS_100OLD, 0, ATA_UDMA5, "730" }, /* 1chip */
89
90 { ATA_SIS635, 0x00, SIS_100NEW, 0, ATA_UDMA5, "635" }, /* 1chip */
91 { ATA_SIS633, 0x00, SIS_100NEW, 0, ATA_UDMA5, "633" }, /* unknown */
92 { ATA_SIS630, 0x30, SIS_100OLD, 0, ATA_UDMA5, "630S"}, /* 1chip */
93 { ATA_SIS630, 0x00, SIS_66, 0, ATA_UDMA4, "630" }, /* 1chip */
94 { ATA_SIS620, 0x00, SIS_66, 0, ATA_UDMA4, "620" }, /* 1chip */
95
96 { ATA_SIS550, 0x00, SIS_66, 0, ATA_UDMA5, "550" },
97 { ATA_SIS540, 0x00, SIS_66, 0, ATA_UDMA4, "540" },
98 { ATA_SIS530, 0x00, SIS_66, 0, ATA_UDMA4, "530" },
99
100 { ATA_SIS5513, 0xc2, SIS_33, 1, ATA_UDMA2, "5513" },
101 { ATA_SIS5513, 0x00, SIS_33, 1, ATA_WDMA2, "5513" },
102 { 0, 0, 0, 0, 0, 0 }};
103 static struct ata_chip_id id[] =
104 {{ ATA_SISSOUTH, 0x10, 0, 0, 0, "" }, { 0, 0, 0, 0, 0, 0 }};
105 char buffer[64];
106 int found = 0;
107
108 if (pci_get_class(dev) != PCIC_STORAGE)
109 return (ENXIO);
110
111 if (pci_get_vendor(dev) != ATA_SIS_ID)
112 return ENXIO;
113
114 if (!(idx = ata_find_chip(dev, ids, -pci_get_slot(dev))))
115 return ENXIO;
116
117 if (idx->cfg2) {
118 u_int8_t reg57 = pci_read_config(dev, 0x57, 1);
119
120 pci_write_config(dev, 0x57, (reg57 & 0x7f), 1);
121 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5518) {
122 found = 1;
123 memcpy(&id[0], idx, sizeof(id[0]));
124 id[0].cfg1 = SIS_133NEW;
125 id[0].max_dma = ATA_UDMA6;
126 sprintf(buffer, "SiS 962/963 %s controller",
127 ata_mode2str(idx->max_dma));
128 }
129 pci_write_config(dev, 0x57, reg57, 1);
130 }
131 if (idx->cfg2 && !found) {
132 u_int8_t reg4a = pci_read_config(dev, 0x4a, 1);
133
134 pci_write_config(dev, 0x4a, (reg4a | 0x10), 1);
135 if (pci_read_config(dev, PCIR_DEVVENDOR, 4) == ATA_SIS5517) {
136 found = 1;
137 if (ata_find_chip(dev, id, pci_get_slot(dev))) {
138 id[0].cfg1 = SIS_133OLD;
139 id[0].max_dma = ATA_UDMA6;
140 } else {
141 id[0].cfg1 = SIS_100NEW;
142 id[0].max_dma = ATA_UDMA5;
143 }
144 sprintf(buffer, "SiS 961 %s controller",ata_mode2str(idx->max_dma));
145 }
146 pci_write_config(dev, 0x4a, reg4a, 1);
147 }
148 if (!found)
149 sprintf(buffer,"SiS %s %s controller",
150 idx->text, ata_mode2str(idx->max_dma));
151 else
152 idx = &id[0];
153
154 device_set_desc_copy(dev, buffer);
155 ctlr->chip = idx;
156 ctlr->chipinit = ata_sis_chipinit;
157 return (BUS_PROBE_LOW_PRIORITY);
158 }
159
160 static int
ata_sis_chipinit(device_t dev)161 ata_sis_chipinit(device_t dev)
162 {
163 struct ata_pci_controller *ctlr = device_get_softc(dev);
164
165 if (ata_setup_interrupt(dev, ata_generic_intr))
166 return ENXIO;
167
168 switch (ctlr->chip->cfg1) {
169 case SIS_33:
170 break;
171 case SIS_66:
172 case SIS_100OLD:
173 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 1) & ~0x04, 1);
174 break;
175 case SIS_100NEW:
176 case SIS_133OLD:
177 pci_write_config(dev, 0x49, pci_read_config(dev, 0x49, 1) & ~0x01, 1);
178 break;
179 case SIS_133NEW:
180 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 2) | 0x0008, 2);
181 pci_write_config(dev, 0x52, pci_read_config(dev, 0x52, 2) | 0x0008, 2);
182 break;
183 case SIS_SATA:
184 ctlr->r_type2 = SYS_RES_IOPORT;
185 ctlr->r_rid2 = PCIR_BAR(5);
186 if ((ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
187 &ctlr->r_rid2, RF_ACTIVE))) {
188 ctlr->ch_attach = ata_sis_ch_attach;
189 ctlr->ch_detach = ata_pci_ch_detach;
190 ctlr->reset = ata_sis_reset;
191 }
192 ctlr->setmode = ata_sata_setmode;
193 ctlr->getrev = ata_sata_getrev;
194 return 0;
195 default:
196 return ENXIO;
197 }
198 ctlr->setmode = ata_sis_setmode;
199 return 0;
200 }
201
202 static int
ata_sis_ch_attach(device_t dev)203 ata_sis_ch_attach(device_t dev)
204 {
205 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
206 struct ata_channel *ch = device_get_softc(dev);
207 int offset = ch->unit << ((ctlr->chip->chipid == ATA_SIS182) ? 5 : 6);
208
209 /* setup the usual register normal pci style */
210 if (ata_pci_ch_attach(dev))
211 return ENXIO;
212
213 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
214 ch->r_io[ATA_SSTATUS].offset = 0x00 + offset;
215 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
216 ch->r_io[ATA_SERROR].offset = 0x04 + offset;
217 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
218 ch->r_io[ATA_SCONTROL].offset = 0x08 + offset;
219 ch->flags |= ATA_NO_SLAVE;
220 ch->flags |= ATA_SATA;
221
222 /* XXX SOS PHY hotplug handling missing in SiS chip ?? */
223 /* XXX SOS unknown how to enable PHY state change interrupt */
224 return 0;
225 }
226
227 static void
ata_sis_reset(device_t dev)228 ata_sis_reset(device_t dev)
229 {
230 struct ata_channel *ch = device_get_softc(dev);
231
232 if (ata_sata_phy_reset(dev, -1, 1))
233 ata_generic_reset(dev);
234 else
235 ch->devices = 0;
236 }
237
238 static int
ata_sis_setmode(device_t dev,int target,int mode)239 ata_sis_setmode(device_t dev, int target, int mode)
240 {
241 device_t parent = device_get_parent(dev);
242 struct ata_pci_controller *ctlr = device_get_softc(parent);
243 struct ata_channel *ch = device_get_softc(dev);
244 int devno = (ch->unit << 1) + target;
245
246 mode = min(mode, ctlr->chip->max_dma);
247
248 if (ctlr->chip->cfg1 == SIS_133NEW) {
249 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
250 pci_read_config(parent, ch->unit ? 0x52 : 0x50,2) & 0x8000) {
251 ata_print_cable(dev, "controller");
252 mode = ATA_UDMA2;
253 }
254 } else {
255 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
256 pci_read_config(parent, 0x48, 1)&(ch->unit ? 0x20 : 0x10)) {
257 ata_print_cable(dev, "controller");
258 mode = ATA_UDMA2;
259 }
260 }
261
262 switch (ctlr->chip->cfg1) {
263 case SIS_133NEW: {
264 static const uint32_t timings[] =
265 { 0x28269008, 0x0c266008, 0x04263008, 0x0c0a3008, 0x05093008,
266 0x22196008, 0x0c0a3008, 0x05093008, 0x050939fc, 0x050936ac,
267 0x0509347c, 0x0509325c, 0x0509323c, 0x0509322c, 0x0509321c};
268 u_int32_t reg;
269
270 reg = (pci_read_config(parent, 0x57, 1)&0x40?0x70:0x40)+(devno<<2);
271 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 4);
272 break;
273 }
274 case SIS_133OLD: {
275 static const uint16_t timings[] =
276 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033, 0x0031,
277 0x8f31, 0x8a31, 0x8731, 0x8531, 0x8331, 0x8231, 0x8131 };
278
279 u_int16_t reg = 0x40 + (devno << 1);
280
281 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
282 break;
283 }
284 case SIS_100NEW: {
285 static const uint16_t timings[] =
286 { 0x00cb, 0x0067, 0x0044, 0x0033, 0x0031, 0x0044, 0x0033,
287 0x0031, 0x8b31, 0x8731, 0x8531, 0x8431, 0x8231, 0x8131 };
288 u_int16_t reg = 0x40 + (devno << 1);
289
290 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
291 break;
292 }
293 case SIS_100OLD:
294 case SIS_66:
295 case SIS_33: {
296 static const uint16_t timings[] =
297 { 0x0c0b, 0x0607, 0x0404, 0x0303, 0x0301, 0x0404, 0x0303,
298 0x0301, 0xf301, 0xd301, 0xb301, 0xa301, 0x9301, 0x8301 };
299 u_int16_t reg = 0x40 + (devno << 1);
300
301 pci_write_config(parent, reg, timings[ata_mode2idx(mode)], 2);
302 break;
303 }
304 }
305 return (mode);
306 }
307
308 ATA_DECLARE_DRIVER(ata_sis);
309