1 /*-
2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
38 #include <sys/lock.h>
39 #include <sys/mutex.h>
40 #include <sys/sema.h>
41 #include <sys/taskqueue.h>
42 #include <vm/uma.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
46 #include <sys/rman.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
51 #include <ata_if.h>
52
53 /* local prototypes */
54 static int ata_ali_chipinit(device_t dev);
55 static int ata_ali_chipdeinit(device_t dev);
56 static int ata_ali_ch_attach(device_t dev);
57 static int ata_ali_sata_ch_attach(device_t dev);
58 static void ata_ali_reset(device_t dev);
59 static int ata_ali_setmode(device_t dev, int target, int mode);
60
61 /* misc defines */
62 #define ALI_OLD 0x01
63 #define ALI_NEW 0x02
64 #define ALI_SATA 0x04
65
66 struct ali_sata_resources {
67 struct resource *bars[4];
68 };
69
70 /*
71 * Acer Labs Inc (ALI) chipset support functions
72 */
73 static int
ata_ali_probe(device_t dev)74 ata_ali_probe(device_t dev)
75 {
76 struct ata_pci_controller *ctlr = device_get_softc(dev);
77 static const struct ata_chip_id ids[] =
78 {{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
79 { ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
80 { ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
81 { ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
82 { ATA_ALI_5228, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5228" },
83 { ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" },
84 { ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" },
85 { ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" },
86 { ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" },
87 { ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" },
88 { 0, 0, 0, 0, 0, 0}};
89
90 if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
91 return ENXIO;
92
93 if (!(ctlr->chip = ata_match_chip(dev, ids)))
94 return ENXIO;
95
96 ata_set_desc(dev);
97 ctlr->chipinit = ata_ali_chipinit;
98 ctlr->chipdeinit = ata_ali_chipdeinit;
99 return (BUS_PROBE_LOW_PRIORITY);
100 }
101
102 static int
ata_ali_chipinit(device_t dev)103 ata_ali_chipinit(device_t dev)
104 {
105 struct ata_pci_controller *ctlr = device_get_softc(dev);
106 struct ali_sata_resources *res;
107 int i, rid;
108
109 if (ata_setup_interrupt(dev, ata_generic_intr))
110 return ENXIO;
111
112 switch (ctlr->chip->cfg2) {
113 case ALI_SATA:
114 ctlr->channels = ctlr->chip->cfg1;
115 ctlr->ch_attach = ata_ali_sata_ch_attach;
116 ctlr->ch_detach = ata_pci_ch_detach;
117 ctlr->setmode = ata_sata_setmode;
118 ctlr->getrev = ata_sata_getrev;
119
120 /* Allocate resources for later use by channel attach routines. */
121 res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
122 for (i = 0; i < 4; i++) {
123 rid = PCIR_BAR(i);
124 res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
125 RF_ACTIVE);
126 if (res->bars[i] == NULL) {
127 device_printf(dev, "Failed to allocate BAR %d\n", i);
128 for (i--; i >=0; i--)
129 bus_release_resource(dev, SYS_RES_IOPORT,
130 PCIR_BAR(i), res->bars[i]);
131 free(res, M_ATAPCI);
132 return ENXIO;
133 }
134 }
135 ctlr->chipset_data = res;
136 break;
137
138 case ALI_NEW:
139 /* use device interrupt as byte count end */
140 pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
141
142 /* enable cable detection and UDMA support on revisions < 0xc7 */
143 if (ctlr->chip->chiprev < 0xc7)
144 pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
145 0x09, 1);
146
147 /* enable ATAPI UDMA mode (even if we are going to do PIO) */
148 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
149 (ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
150
151 /* only chips with revision > 0xc4 can do 48bit DMA */
152 if (ctlr->chip->chiprev <= 0xc4)
153 device_printf(dev,
154 "using PIO transfers above 137GB as workaround for "
155 "48bit DMA access bug, expect reduced performance\n");
156 ctlr->ch_attach = ata_ali_ch_attach;
157 ctlr->ch_detach = ata_pci_ch_detach;
158 ctlr->reset = ata_ali_reset;
159 ctlr->setmode = ata_ali_setmode;
160 break;
161
162 case ALI_OLD:
163 /* deactivate the ATAPI FIFO and enable ATAPI UDMA */
164 pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
165 ctlr->setmode = ata_ali_setmode;
166 break;
167 }
168 return 0;
169 }
170
171 static int
ata_ali_chipdeinit(device_t dev)172 ata_ali_chipdeinit(device_t dev)
173 {
174 struct ata_pci_controller *ctlr = device_get_softc(dev);
175 struct ali_sata_resources *res;
176 int i;
177
178 if (ctlr->chip->cfg2 == ALI_SATA) {
179 res = ctlr->chipset_data;
180 for (i = 0; i < 4; i++) {
181 if (res->bars[i] != NULL) {
182 bus_release_resource(dev, SYS_RES_IOPORT,
183 PCIR_BAR(i), res->bars[i]);
184 }
185 }
186 free(res, M_ATAPCI);
187 ctlr->chipset_data = NULL;
188 }
189 return (0);
190 }
191
192 static int
ata_ali_ch_attach(device_t dev)193 ata_ali_ch_attach(device_t dev)
194 {
195 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
196 struct ata_channel *ch = device_get_softc(dev);
197
198 /* setup the usual register normal pci style */
199 if (ata_pci_ch_attach(dev))
200 return ENXIO;
201
202 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
203 ch->flags |= ATA_CHECKS_CABLE;
204 /* older chips can't do 48bit DMA transfers */
205 if (ctlr->chip->chiprev <= 0xc4) {
206 ch->flags |= ATA_NO_48BIT_DMA;
207 if (ch->dma.max_iosize > 256 * 512)
208 ch->dma.max_iosize = 256 * 512;
209 }
210 if (ctlr->chip->cfg2 & ALI_NEW)
211 ch->flags |= ATA_NO_ATAPI_DMA;
212
213 return 0;
214 }
215
216 static int
ata_ali_sata_ch_attach(device_t dev)217 ata_ali_sata_ch_attach(device_t dev)
218 {
219 device_t parent = device_get_parent(dev);
220 struct ata_pci_controller *ctlr = device_get_softc(parent);
221 struct ata_channel *ch = device_get_softc(dev);
222 struct ali_sata_resources *res;
223 struct resource *io = NULL, *ctlio = NULL;
224 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
225 int i;
226
227 res = ctlr->chipset_data;
228 if (unit01) {
229 io = res->bars[2];
230 ctlio = res->bars[3];
231 } else {
232 io = res->bars[0];
233 ctlio = res->bars[1];
234 }
235 ata_pci_dmainit(dev);
236 for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
237 ch->r_io[i].res = io;
238 ch->r_io[i].offset = i + (unit10 ? 8 : 0);
239 }
240 ch->r_io[ATA_CONTROL].res = ctlio;
241 ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
242 ch->r_io[ATA_IDX_ADDR].res = io;
243 ata_default_registers(dev);
244 if (ctlr->r_res1) {
245 for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
246 ch->r_io[i].res = ctlr->r_res1;
247 ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
248 }
249 }
250 ch->flags |= ATA_NO_SLAVE;
251 ch->flags |= ATA_SATA;
252
253 /* XXX SOS PHY handling awkward in ALI chip not supported yet */
254 ata_pci_hw(dev);
255 return 0;
256 }
257
258 static void
ata_ali_reset(device_t dev)259 ata_ali_reset(device_t dev)
260 {
261 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
262 struct ata_channel *ch = device_get_softc(dev);
263 device_t *children;
264 int nchildren, i;
265
266 ata_generic_reset(dev);
267
268 /*
269 * workaround for datacorruption bug found on at least SUN Blade-100
270 * find the ISA function on the southbridge and disable then enable
271 * the ATA channel tristate buffer
272 */
273 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
274 if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
275 for (i = 0; i < nchildren; i++) {
276 if (pci_get_devid(children[i]) == ATA_ALI_1533) {
277 pci_write_config(children[i], 0x58,
278 pci_read_config(children[i], 0x58, 1) &
279 ~(0x04 << ch->unit), 1);
280 pci_write_config(children[i], 0x58,
281 pci_read_config(children[i], 0x58, 1) |
282 (0x04 << ch->unit), 1);
283 break;
284 }
285 }
286 free(children, M_TEMP);
287 }
288 }
289 }
290
291 static int
ata_ali_setmode(device_t dev,int target,int mode)292 ata_ali_setmode(device_t dev, int target, int mode)
293 {
294 device_t parent = device_get_parent(dev);
295 struct ata_pci_controller *ctlr = device_get_softc(parent);
296 struct ata_channel *ch = device_get_softc(dev);
297 int devno = (ch->unit << 1) + target;
298 int piomode;
299 static const uint32_t piotimings[] =
300 { 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
301 0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
302 static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f,
303 0x0d};
304 uint32_t word54;
305
306 mode = min(mode, ctlr->chip->max_dma);
307
308 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
309 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
310 pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
311 ata_print_cable(dev, "controller");
312 mode = ATA_UDMA2;
313 }
314 }
315 if (ctlr->chip->cfg2 & ALI_OLD) {
316 /* doesn't support ATAPI DMA on write */
317 ch->flags |= ATA_ATAPI_DMA_RO;
318 if (ch->devices & ATA_ATAPI_MASTER &&
319 ch->devices & ATA_ATAPI_SLAVE) {
320 /* doesn't support ATAPI DMA on two ATAPI devices */
321 device_printf(dev, "two atapi devices on this channel,"
322 " no DMA\n");
323 mode = min(mode, ATA_PIO_MAX);
324 }
325 }
326 /* Set UDMA mode */
327 word54 = pci_read_config(parent, 0x54, 4);
328 if (mode >= ATA_UDMA0) {
329 word54 &= ~(0x000f000f << (devno << 2));
330 word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
331 piomode = ATA_PIO4;
332 }
333 else {
334 word54 &= ~(0x0008000f << (devno << 2));
335 piomode = mode;
336 }
337 pci_write_config(parent, 0x54, word54, 4);
338 /* Set PIO/WDMA mode */
339 pci_write_config(parent, 0x58 + (ch->unit << 2),
340 piotimings[ata_mode2idx(piomode)], 4);
341 return (mode);
342 }
343
344 ATA_DECLARE_DRIVER(ata_ali);
345