1 /*-
2 * Copyright (c) 2014 Andrew Turner
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29 #ifndef _MACHINE_CPUFUNC_H_
30 #define _MACHINE_CPUFUNC_H_
31
32 #ifdef _KERNEL
33
34 #include <machine/armreg.h>
35
36 static __inline void
breakpoint(void)37 breakpoint(void)
38 {
39
40 __asm("brk #0");
41 }
42
43 static __inline register_t
dbg_disable(void)44 dbg_disable(void)
45 {
46 uint32_t ret;
47
48 __asm __volatile(
49 "mrs %x0, daif \n"
50 "msr daifset, #8 \n"
51 : "=&r" (ret));
52
53 return (ret);
54 }
55
56 static __inline void
dbg_enable(void)57 dbg_enable(void)
58 {
59
60 __asm __volatile("msr daifclr, #8");
61 }
62
63 static __inline register_t
intr_disable(void)64 intr_disable(void)
65 {
66 /* DAIF is a 32-bit register */
67 uint32_t ret;
68
69 __asm __volatile(
70 "mrs %x0, daif \n"
71 "msr daifset, #2 \n"
72 : "=&r" (ret));
73
74 return (ret);
75 }
76
77 static __inline void
intr_restore(register_t s)78 intr_restore(register_t s)
79 {
80
81 WRITE_SPECIALREG(daif, s);
82 }
83
84 static __inline void
intr_enable(void)85 intr_enable(void)
86 {
87
88 __asm __volatile("msr daifclr, #2");
89 }
90
91 static __inline register_t
get_midr(void)92 get_midr(void)
93 {
94 uint64_t midr;
95
96 midr = READ_SPECIALREG(midr_el1);
97
98 return (midr);
99 }
100
101 static __inline register_t
get_mpidr(void)102 get_mpidr(void)
103 {
104 uint64_t mpidr;
105
106 mpidr = READ_SPECIALREG(mpidr_el1);
107
108 return (mpidr);
109 }
110
111 static __inline void
clrex(void)112 clrex(void)
113 {
114
115 /*
116 * Ensure compiler barrier, otherwise the monitor clear might
117 * occur too late for us ?
118 */
119 __asm __volatile("clrex" : : : "memory");
120 }
121
122 #define cpu_nullop() arm64_nullop()
123 #define cpufunc_nullop() arm64_nullop()
124 #define cpu_setttb(a) arm64_setttb(a)
125
126 #define cpu_tlb_flushID() arm64_tlb_flushID()
127 #define cpu_tlb_flushID_SE(e) arm64_tlb_flushID_SE(e)
128
129 #define cpu_dcache_wbinv_range(a, s) arm64_dcache_wbinv_range((a), (s))
130 #define cpu_dcache_inv_range(a, s) arm64_dcache_inv_range((a), (s))
131 #define cpu_dcache_wb_range(a, s) arm64_dcache_wb_range((a), (s))
132
133 #define cpu_idcache_wbinv_range(a, s) arm64_idcache_wbinv_range((a), (s))
134 #define cpu_icache_sync_range(a, s) arm64_icache_sync_range((a), (s))
135
136 void arm64_nullop(void);
137 void arm64_setttb(vm_offset_t);
138 void arm64_tlb_flushID(void);
139 void arm64_tlb_flushID_SE(vm_offset_t);
140 void arm64_icache_sync_range(vm_offset_t, vm_size_t);
141 void arm64_idcache_wbinv_range(vm_offset_t, vm_size_t);
142 void arm64_dcache_wbinv_range(vm_offset_t, vm_size_t);
143 void arm64_dcache_inv_range(vm_offset_t, vm_size_t);
144 void arm64_dcache_wb_range(vm_offset_t, vm_size_t);
145
146 #endif /* _KERNEL */
147 #endif /* _MACHINE_CPUFUNC_H_ */
148