1 /*-
2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 */
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include <sys/stdint.h>
31 #include <sys/stddef.h>
32 #include <sys/param.h>
33 #include <sys/queue.h>
34 #include <sys/types.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/bus.h>
38 #include <sys/module.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/condvar.h>
42 #include <sys/sysctl.h>
43 #include <sys/rman.h>
44 #include <sys/sx.h>
45 #include <sys/unistd.h>
46 #include <sys/callout.h>
47 #include <sys/malloc.h>
48 #include <sys/priv.h>
49
50 #include <sys/kdb.h>
51
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
54
55 #include <dev/usb/usb.h>
56 #include <dev/usb/usbdi.h>
57
58 #include <dev/usb/usb_core.h>
59 #include <dev/usb/usb_busdma.h>
60 #include <dev/usb/usb_process.h>
61 #include <dev/usb/usb_util.h>
62
63 #include <dev/usb/usb_controller.h>
64 #include <dev/usb/usb_bus.h>
65 #include <dev/usb/controller/ohci.h>
66 #include <dev/usb/controller/ohcireg.h>
67
68 #include <arm/lpc/lpcreg.h>
69 #include <arm/lpc/lpcvar.h>
70
71 #define I2C_START_BIT (1 << 8)
72 #define I2C_STOP_BIT (1 << 9)
73 #define I2C_READ 0x01
74 #define I2C_WRITE 0x00
75 #define DUMMY_BYTE 0x55
76
77 #define lpc_otg_read_4(_sc, _reg) \
78 bus_space_read_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg)
79 #define lpc_otg_write_4(_sc, _reg, _value) \
80 bus_space_write_4(_sc->sc_io_tag, _sc->sc_io_hdl, _reg, _value)
81 #define lpc_otg_wait_write_4(_sc, _wreg, _sreg, _value) \
82 do { \
83 lpc_otg_write_4(_sc, _wreg, _value); \
84 while ((lpc_otg_read_4(_sc, _sreg) & _value) != _value); \
85 } while (0);
86
87 static int lpc_ohci_probe(device_t dev);
88 static int lpc_ohci_attach(device_t dev);
89 static int lpc_ohci_detach(device_t dev);
90
91 static void lpc_otg_i2c_reset(struct ohci_softc *);
92
93 static int lpc_isp3101_read(struct ohci_softc *, int);
94 static void lpc_isp3101_write(struct ohci_softc *, int, int);
95 static void lpc_isp3101_clear(struct ohci_softc *, int, int);
96 static void lpc_isp3101_configure(device_t dev, struct ohci_softc *);
97
98 static int
lpc_ohci_probe(device_t dev)99 lpc_ohci_probe(device_t dev)
100 {
101
102 if (!ofw_bus_status_okay(dev))
103 return (ENXIO);
104
105 if (!ofw_bus_is_compatible(dev, "lpc,usb-ohci"))
106 return (ENXIO);
107
108 device_set_desc(dev, "LPC32x0 USB OHCI controller");
109 return (BUS_PROBE_DEFAULT);
110 }
111
112 static int
lpc_ohci_attach(device_t dev)113 lpc_ohci_attach(device_t dev)
114 {
115 struct ohci_softc *sc = device_get_softc(dev);
116 int err;
117 int rid;
118 int i = 0;
119 uint32_t usbctrl;
120 uint32_t otgstatus;
121
122 sc->sc_bus.parent = dev;
123 sc->sc_bus.devices = sc->sc_devices;
124 sc->sc_bus.devices_max = OHCI_MAX_DEVICES;
125 sc->sc_bus.dma_bits = 32;
126
127 if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev),
128 &ohci_iterate_hw_softc))
129 return (ENOMEM);
130
131 rid = 0;
132 sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
133 if (!sc->sc_io_res) {
134 device_printf(dev, "cannot map OHCI register space\n");
135 goto fail;
136 }
137
138 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
139 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
140 sc->sc_io_size = rman_get_size(sc->sc_io_res);
141
142 rid = 0;
143 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE);
144 if (sc->sc_irq_res == NULL) {
145 device_printf(dev, "cannot allocate interrupt\n");
146 goto fail;
147 }
148
149 sc->sc_bus.bdev = device_add_child(dev, "usbus", -1);
150 if (!(sc->sc_bus.bdev))
151 goto fail;
152
153 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
154 strlcpy(sc->sc_vendor, "NXP", sizeof(sc->sc_vendor));
155
156 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
157 NULL, (void *)ohci_interrupt, sc, &sc->sc_intr_hdl);
158 if (err) {
159 sc->sc_intr_hdl = NULL;
160 goto fail;
161 }
162
163 usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL);
164 usbctrl |= LPC_CLKPWR_USB_CTRL_SLAVE_HCLK | LPC_CLKPWR_USB_CTRL_BUSKEEPER;
165 lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
166
167 /* Enable OTG I2C clock */
168 lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL,
169 LPC_OTG_CLOCK_STATUS, LPC_OTG_CLOCK_CTRL_I2C_EN);
170
171 /* Reset OTG I2C bus */
172 lpc_otg_i2c_reset(sc);
173
174 lpc_isp3101_configure(dev, sc);
175
176 /* Configure PLL */
177 usbctrl &= ~(LPC_CLKPWR_USB_CTRL_CLK_EN1 | LPC_CLKPWR_USB_CTRL_CLK_EN2);
178 lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
179
180 usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN1;
181 lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
182
183 usbctrl |= LPC_CLKPWR_USB_CTRL_FDBKDIV(192-1);
184 usbctrl |= LPC_CLKPWR_USB_CTRL_POSTDIV(1);
185 usbctrl |= LPC_CLKPWR_USB_CTRL_PLL_PDOWN;
186
187 lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
188 do {
189 usbctrl = lpc_pwr_read(dev, LPC_CLKPWR_USB_CTRL);
190 if (i++ > 100000) {
191 device_printf(dev, "USB OTG PLL doesn't lock!\n");
192 goto fail;
193 }
194 } while ((usbctrl & LPC_CLKPWR_USB_CTRL_PLL_LOCK) == 0);
195
196 usbctrl |= LPC_CLKPWR_USB_CTRL_CLK_EN2;
197 usbctrl |= LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN;
198 lpc_pwr_write(dev, LPC_CLKPWR_USB_CTRL, usbctrl);
199 lpc_otg_wait_write_4(sc, LPC_OTG_CLOCK_CTRL, LPC_OTG_CLOCK_STATUS,
200 (LPC_OTG_CLOCK_CTRL_AHB_EN | LPC_OTG_CLOCK_CTRL_OTG_EN |
201 LPC_OTG_CLOCK_CTRL_I2C_EN | LPC_OTG_CLOCK_CTRL_HOST_EN));
202
203 otgstatus = lpc_otg_read_4(sc, LPC_OTG_STATUS);
204 lpc_otg_write_4(sc, LPC_OTG_STATUS, otgstatus |
205 LPC_OTG_STATUS_HOST_EN);
206
207 lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1,
208 LPC_ISP3101_OTG1_VBUS_DRV);
209
210 err = ohci_init(sc);
211 if (err)
212 goto fail;
213
214 err = device_probe_and_attach(sc->sc_bus.bdev);
215 if (err)
216 goto fail;
217
218 return (0);
219
220 fail:
221 if (sc->sc_intr_hdl)
222 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intr_hdl);
223 if (sc->sc_irq_res)
224 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
225 if (sc->sc_io_res)
226 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_io_res);
227
228 return (ENXIO);
229 }
230
231 static int
lpc_isp3101_read(struct ohci_softc * sc,int reg)232 lpc_isp3101_read(struct ohci_softc *sc, int reg)
233 {
234 int status;
235 int i = 0;
236
237 lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX,
238 (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT);
239 lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, reg);
240 lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, (LPC_ISP3101_I2C_ADDR << 1) |
241 I2C_START_BIT | I2C_READ);
242 lpc_otg_write_4(sc, LPC_OTG_I2C_TXRX, I2C_STOP_BIT | DUMMY_BYTE);
243
244 do {
245 status = lpc_otg_read_4(sc, LPC_OTG_I2C_STATUS);
246 i++;
247 } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000);
248
249 lpc_otg_write_4(sc, LPC_OTG_I2C_STATUS, LPC_OTG_I2C_STATUS_TDI);
250
251 return (lpc_otg_read_4(sc, LPC_OTG_I2C_TXRX) & 0xff);
252 }
253
254 static void
lpc_otg_i2c_reset(struct ohci_softc * sc)255 lpc_otg_i2c_reset(struct ohci_softc *sc)
256 {
257 int ctrl;
258 int i = 0;
259
260 lpc_otg_write_4(sc, LPC_OTG_I2C_CLKHI, 0x3f);
261 lpc_otg_write_4(sc, LPC_OTG_I2C_CLKLO, 0x3f);
262
263 ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL);
264 lpc_otg_write_4(sc, LPC_OTG_I2C_CTRL, ctrl | LPC_OTG_I2C_CTRL_SRST);
265
266 do {
267 ctrl = lpc_otg_read_4(sc, LPC_OTG_I2C_CTRL);
268 i++;
269 } while (ctrl & LPC_OTG_I2C_CTRL_SRST);
270 }
271
272 static void
lpc_isp3101_write(struct ohci_softc * sc,int reg,int value)273 lpc_isp3101_write(struct ohci_softc *sc, int reg, int value)
274 {
275 int status;
276 int i = 0;
277
278 bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
279 (LPC_ISP3101_I2C_ADDR << 1) | I2C_START_BIT);
280 bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
281 (reg | I2C_WRITE));
282 bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_TXRX,
283 (value | I2C_STOP_BIT));
284
285 do {
286 status = bus_space_read_4(sc->sc_io_tag, sc->sc_io_hdl,
287 LPC_OTG_I2C_STATUS);
288 i++;
289 } while ((status & LPC_OTG_I2C_STATUS_TDI) == 0 || i < 100000);
290
291 bus_space_write_4(sc->sc_io_tag, sc->sc_io_hdl, LPC_OTG_I2C_STATUS,
292 LPC_OTG_I2C_STATUS_TDI);
293 }
294
295 static __inline void
lpc_isp3101_clear(struct ohci_softc * sc,int reg,int value)296 lpc_isp3101_clear(struct ohci_softc *sc, int reg, int value)
297 {
298 lpc_isp3101_write(sc, (reg | LPC_ISP3101_REG_CLEAR_ADDR), value);
299 }
300
301 static void
lpc_isp3101_configure(device_t dev,struct ohci_softc * sc)302 lpc_isp3101_configure(device_t dev, struct ohci_softc *sc)
303 {
304 lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_UART_EN);
305 lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_1, ~LPC_ISP3101_MC1_SPEED_REG);
306 lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_SPEED_REG);
307 lpc_isp3101_clear(sc, LPC_ISP3101_MODE_CONTROL_2, ~0);
308 lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_2,
309 (LPC_ISP3101_MC2_BI_DI | LPC_ISP3101_MC2_PSW_EN
310 | LPC_ISP3101_MC2_SPD_SUSP_CTRL));
311
312 lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1, ~0);
313 lpc_isp3101_write(sc, LPC_ISP3101_MODE_CONTROL_1, LPC_ISP3101_MC1_DAT_SE0);
314 lpc_isp3101_write(sc, LPC_ISP3101_OTG_CONTROL_1,
315 (LPC_ISP3101_OTG1_DM_PULLDOWN | LPC_ISP3101_OTG1_DP_PULLDOWN));
316
317 lpc_isp3101_clear(sc, LPC_ISP3101_OTG_CONTROL_1,
318 (LPC_ISP3101_OTG1_DM_PULLUP | LPC_ISP3101_OTG1_DP_PULLUP));
319
320 lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_LATCH, ~0);
321 lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_FALLING, ~0);
322 lpc_isp3101_clear(sc, LPC_ISP3101_OTG_INTR_RISING, ~0);
323
324 device_printf(dev,
325 "ISP3101 PHY <vendor:0x%04x, product:0x%04x, version:0x%04x>\n",
326 (lpc_isp3101_read(sc, 0x00) | (lpc_isp3101_read(sc, 0x01) << 8)),
327 (lpc_isp3101_read(sc, 0x03) | (lpc_isp3101_read(sc, 0x04) << 8)),
328 (lpc_isp3101_read(sc, 0x14) | (lpc_isp3101_read(sc, 0x15) << 8)));
329 }
330
331 static int
lpc_ohci_detach(device_t dev)332 lpc_ohci_detach(device_t dev)
333 {
334 return (0);
335 }
336
337
338 static device_method_t lpc_ohci_methods[] = {
339 /* Device interface */
340 DEVMETHOD(device_probe, lpc_ohci_probe),
341 DEVMETHOD(device_attach, lpc_ohci_attach),
342 DEVMETHOD(device_detach, lpc_ohci_detach),
343 DEVMETHOD(device_shutdown, bus_generic_shutdown),
344
345 /* Bus interface */
346 DEVMETHOD(bus_print_child, bus_generic_print_child),
347 { 0, 0 }
348 };
349
350 static driver_t lpc_ohci_driver = {
351 "ohci",
352 lpc_ohci_methods,
353 sizeof(struct ohci_softc),
354 };
355
356 static devclass_t lpc_ohci_devclass;
357
358 DRIVER_MODULE(ohci, simplebus, lpc_ohci_driver, lpc_ohci_devclass, 0, 0);
359 MODULE_DEPEND(ohci, usb, 1, 1, 1);
360