1 /* 2 * This file is part of the Chelsio T4 Ethernet driver. 3 * 4 * Copyright (C) 2003-2014 Chelsio Communications. All rights reserved. 5 * 6 * This program is distributed in the hope that it will be useful, but WITHOUT 7 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 8 * FITNESS FOR A PARTICULAR PURPOSE. See the LICENSE file included in this 9 * release for licensing terms and conditions. 10 */ 11 #ifndef __T4_PCI_ID_TBL_H__ 12 #define __T4_PCI_ID_TBL_H__ 13 14 /* 15 * The Os-Dependent code can defined cpp macros for creating a PCI Device ID 16 * Table. This is useful because it allows the PCI ID Table to be maintained 17 * in a single place and all supporting OSes to get new PCI Device IDs 18 * automatically. 19 * 20 * The macros are: 21 * 22 * CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN 23 * -- Used to start the definition of the PCI ID Table. 24 * 25 * CH_PCI_DEVICE_ID_FUNCTION 26 * -- The PCI Function Number to use in the PCI Device ID Table. "0" 27 * -- for drivers attaching to PF0-3, "4" for drivers attaching to PF4, 28 * -- "8" for drivers attaching to SR-IOV Virtual Functions, etc. 29 * 30 * CH_PCI_DEVICE_ID_FUNCTION2 [optional] 31 * -- If defined, create a PCI Device ID Table with both 32 * -- CH_PCI_DEVICE_ID_FUNCTION and CH_PCI_DEVICE_ID_FUNCTION2 populated. 33 * 34 * CH_PCI_ID_TABLE_ENTRY(DeviceID) 35 * -- Used for the individual PCI Device ID entries. Note that we will 36 * -- be adding a trailing comma (",") after all of the entries (and 37 * -- between the pairs of entries if CH_PCI_DEVICE_ID_FUNCTION2 is defined). 38 * 39 * CH_PCI_DEVICE_ID_TABLE_DEFINE_END 40 * -- Used to finish the definition of the PCI ID Table. Note that we 41 * -- will be adding a trailing semi-colon (";") here. 42 * 43 * CH_PCI_DEVICE_ID_BYPASS_SUPPORTED [optional] 44 * -- If defined, indicates that the OS Driver has support for Bypass 45 * -- Adapters. 46 */ 47 #ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN 48 49 /* 50 * Some sanity checks ... 51 */ 52 #ifndef CH_PCI_DEVICE_ID_FUNCTION 53 #error CH_PCI_DEVICE_ID_FUNCTION not defined! 54 #endif 55 #ifndef CH_PCI_ID_TABLE_ENTRY 56 #error CH_PCI_ID_TABLE_ENTRY not defined! 57 #endif 58 #ifndef CH_PCI_DEVICE_ID_TABLE_DEFINE_END 59 #error CH_PCI_DEVICE_ID_TABLE_DEFINE_END not defined! 60 #endif 61 62 /* 63 * T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where: 64 * 65 * V = "4" for T4; "5" for T5, etc. 66 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs 67 * PP = adapter product designation 68 * 69 * We use this consistency in order to create the proper PCI Device IDs 70 * for the specified CH_PCI_DEVICE_ID_FUNCTION. 71 */ 72 #ifndef CH_PCI_DEVICE_ID_FUNCTION2 73 #define CH_PCI_ID_TABLE_FENTRY(__DeviceID) \ 74 CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \ 75 ((CH_PCI_DEVICE_ID_FUNCTION) << 8)) 76 #else 77 #define CH_PCI_ID_TABLE_FENTRY(__DeviceID) \ 78 CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \ 79 ((CH_PCI_DEVICE_ID_FUNCTION) << 8)), \ 80 CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \ 81 ((CH_PCI_DEVICE_ID_FUNCTION2) << 8)) 82 #endif 83 84 /* Note : The comments against each entry are used by the scripts in the vmware drivers 85 * to correctly generate the pciid xml file, do not change the format currently used. 86 */ 87 88 CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN 89 /* 90 * FPGAs: 91 * 92 * Unfortunately the FPGA PCI Device IDs don't follow the ASIC PCI 93 * Device ID numbering convetions for the Physical Functions. 94 */ 95 #if CH_PCI_DEVICE_ID_FUNCTION != 8 96 CH_PCI_ID_TABLE_ENTRY(0xa000), /* PE10K FPGA */ 97 CH_PCI_ID_TABLE_ENTRY(0xb000), /* PF0 T5 PE10K5 FPGA */ 98 CH_PCI_ID_TABLE_ENTRY(0xb001), /* PF0 T5 PE10K FPGA */ 99 #else 100 CH_PCI_ID_TABLE_FENTRY(0xa000), /* PE10K FPGA */ 101 CH_PCI_ID_TABLE_FENTRY(0xb000), /* PF0 T5 PE10K5 FPGA */ 102 CH_PCI_ID_TABLE_FENTRY(0xb001), /* PF0 T5 PE10K FPGA */ 103 #endif 104 105 /* 106 * These FPGAs seem to be used only by the csiostor driver 107 */ 108 #if ((CH_PCI_DEVICE_ID_FUNCTION == 5) || (CH_PCI_DEVICE_ID_FUNCTION == 6)) 109 CH_PCI_ID_TABLE_ENTRY(0xa001), /* PF1 PE10K FPGA FCOE */ 110 CH_PCI_ID_TABLE_ENTRY(0xa002), /* PE10K FPGA iSCSI */ 111 #endif 112 113 /* 114 * T4 adapters: 115 */ 116 CH_PCI_ID_TABLE_FENTRY(0x4000), /* T440-dbg */ 117 CH_PCI_ID_TABLE_FENTRY(0x4001), /* T420-cr */ 118 CH_PCI_ID_TABLE_FENTRY(0x4002), /* T422-cr */ 119 CH_PCI_ID_TABLE_FENTRY(0x4003), /* T440-cr */ 120 CH_PCI_ID_TABLE_FENTRY(0x4004), /* T420-bch */ 121 CH_PCI_ID_TABLE_FENTRY(0x4005), /* T440-bch */ 122 CH_PCI_ID_TABLE_FENTRY(0x4006), /* T440-ch */ 123 CH_PCI_ID_TABLE_FENTRY(0x4007), /* T420-so */ 124 CH_PCI_ID_TABLE_FENTRY(0x4008), /* T420-cx */ 125 CH_PCI_ID_TABLE_FENTRY(0x4009), /* T420-bt */ 126 CH_PCI_ID_TABLE_FENTRY(0x400a), /* T404-bt */ 127 #ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED 128 CH_PCI_ID_TABLE_FENTRY(0x400b), /* B420-sr */ 129 CH_PCI_ID_TABLE_FENTRY(0x400c), /* B404-bt */ 130 #endif 131 CH_PCI_ID_TABLE_FENTRY(0x400d), /* T480-cr */ 132 CH_PCI_ID_TABLE_FENTRY(0x400e), /* T440-LP-cr */ 133 CH_PCI_ID_TABLE_FENTRY(0x4080), /* Custom T480-cr */ 134 CH_PCI_ID_TABLE_FENTRY(0x4081), /* Custom T440-cr */ 135 CH_PCI_ID_TABLE_FENTRY(0x4082), /* Custom T420-cr */ 136 CH_PCI_ID_TABLE_FENTRY(0x4083), /* Custom T420-xaui */ 137 CH_PCI_ID_TABLE_FENTRY(0x4084), /* Custom T440-cr */ 138 CH_PCI_ID_TABLE_FENTRY(0x4085), /* Custom T420-cr */ 139 CH_PCI_ID_TABLE_FENTRY(0x4086), /* Custom T440-bt */ 140 CH_PCI_ID_TABLE_FENTRY(0x4087), /* Custom T440-cr */ 141 CH_PCI_ID_TABLE_FENTRY(0x4088), /* Custom T440 2-xaui, 2-xfi */ 142 143 /* 144 * T5 adapters: 145 */ 146 CH_PCI_ID_TABLE_FENTRY(0x5000), /* T580-dbg */ 147 CH_PCI_ID_TABLE_FENTRY(0x5001), /* T520-cr */ 148 CH_PCI_ID_TABLE_FENTRY(0x5002), /* T522-cr */ 149 CH_PCI_ID_TABLE_FENTRY(0x5003), /* T540-cr */ 150 CH_PCI_ID_TABLE_FENTRY(0x5004), /* T520-bch */ 151 CH_PCI_ID_TABLE_FENTRY(0x5005), /* T540-bch */ 152 CH_PCI_ID_TABLE_FENTRY(0x5006), /* T540-ch */ 153 CH_PCI_ID_TABLE_FENTRY(0x5007), /* T520-so */ 154 CH_PCI_ID_TABLE_FENTRY(0x5008), /* T520-cx */ 155 CH_PCI_ID_TABLE_FENTRY(0x5009), /* T520-bt */ 156 CH_PCI_ID_TABLE_FENTRY(0x500a), /* T504-bt */ 157 #ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED 158 CH_PCI_ID_TABLE_FENTRY(0x500b), /* B520-sr */ 159 CH_PCI_ID_TABLE_FENTRY(0x500c), /* B504-bt */ 160 #endif 161 CH_PCI_ID_TABLE_FENTRY(0x500d), /* T580-cr */ 162 CH_PCI_ID_TABLE_FENTRY(0x500e), /* T540-LP-cr */ 163 CH_PCI_ID_TABLE_FENTRY(0x5010), /* T580-LP-cr */ 164 CH_PCI_ID_TABLE_FENTRY(0x5011), /* T520-LL-cr */ 165 CH_PCI_ID_TABLE_FENTRY(0x5012), /* T560-cr */ 166 CH_PCI_ID_TABLE_FENTRY(0x5013), /* T580-chr */ 167 CH_PCI_ID_TABLE_FENTRY(0x5014), /* T580-so */ 168 CH_PCI_ID_TABLE_FENTRY(0x5015), /* T502-bt */ 169 CH_PCI_ID_TABLE_FENTRY(0x5080), /* Custom T540-cr */ 170 CH_PCI_ID_TABLE_FENTRY(0x5081), /* Custom T540-LL-cr */ 171 CH_PCI_DEVICE_ID_TABLE_DEFINE_END; 172 173 #endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */ 174 175 #endif /* __T4_PCI_ID_TBL_H__ */ 176