1 //===-- lldb-arm-register-enums.h -----------------------------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #ifndef lldb_arm_register_enums_h 11 #define lldb_arm_register_enums_h 12 13 namespace lldb_private 14 { 15 // LLDB register codes (e.g. RegisterKind == eRegisterKindLLDB) 16 17 //--------------------------------------------------------------------------- 18 // Internal codes for all ARM registers. 19 //--------------------------------------------------------------------------- 20 enum 21 { 22 k_first_gpr_arm = 0, 23 gpr_r0_arm = k_first_gpr_arm, 24 gpr_r1_arm, 25 gpr_r2_arm, 26 gpr_r3_arm, 27 gpr_r4_arm, 28 gpr_r5_arm, 29 gpr_r6_arm, 30 gpr_r7_arm, 31 gpr_r8_arm, 32 gpr_r9_arm, 33 gpr_r10_arm, 34 gpr_r11_arm, 35 gpr_r12_arm, 36 gpr_r13_arm, gpr_sp_arm = gpr_r13_arm, 37 gpr_r14_arm, gpr_lr_arm = gpr_r14_arm, 38 gpr_r15_arm, gpr_pc_arm = gpr_r15_arm, 39 gpr_cpsr_arm, 40 41 k_last_gpr_arm = gpr_cpsr_arm, 42 43 k_first_fpr_arm, 44 fpu_s0_arm = k_first_fpr_arm, 45 fpu_s1_arm, 46 fpu_s2_arm, 47 fpu_s3_arm, 48 fpu_s4_arm, 49 fpu_s5_arm, 50 fpu_s6_arm, 51 fpu_s7_arm, 52 fpu_s8_arm, 53 fpu_s9_arm, 54 fpu_s10_arm, 55 fpu_s11_arm, 56 fpu_s12_arm, 57 fpu_s13_arm, 58 fpu_s14_arm, 59 fpu_s15_arm, 60 fpu_s16_arm, 61 fpu_s17_arm, 62 fpu_s18_arm, 63 fpu_s19_arm, 64 fpu_s20_arm, 65 fpu_s21_arm, 66 fpu_s22_arm, 67 fpu_s23_arm, 68 fpu_s24_arm, 69 fpu_s25_arm, 70 fpu_s26_arm, 71 fpu_s27_arm, 72 fpu_s28_arm, 73 fpu_s29_arm, 74 fpu_s30_arm, 75 fpu_s31_arm, 76 fpu_fpscr_arm, 77 k_last_fpr_arm = fpu_fpscr_arm, 78 exc_exception_arm, 79 exc_fsr_arm, 80 exc_far_arm, 81 82 dbg_bvr0_arm, 83 dbg_bvr1_arm, 84 dbg_bvr2_arm, 85 dbg_bvr3_arm, 86 dbg_bvr4_arm, 87 dbg_bvr5_arm, 88 dbg_bvr6_arm, 89 dbg_bvr7_arm, 90 dbg_bvr8_arm, 91 dbg_bvr9_arm, 92 dbg_bvr10_arm, 93 dbg_bvr11_arm, 94 dbg_bvr12_arm, 95 dbg_bvr13_arm, 96 dbg_bvr14_arm, 97 dbg_bvr15_arm, 98 dbg_bcr0_arm, 99 dbg_bcr1_arm, 100 dbg_bcr2_arm, 101 dbg_bcr3_arm, 102 dbg_bcr4_arm, 103 dbg_bcr5_arm, 104 dbg_bcr6_arm, 105 dbg_bcr7_arm, 106 dbg_bcr8_arm, 107 dbg_bcr9_arm, 108 dbg_bcr10_arm, 109 dbg_bcr11_arm, 110 dbg_bcr12_arm, 111 dbg_bcr13_arm, 112 dbg_bcr14_arm, 113 dbg_bcr15_arm, 114 dbg_wvr0_arm, 115 dbg_wvr1_arm, 116 dbg_wvr2_arm, 117 dbg_wvr3_arm, 118 dbg_wvr4_arm, 119 dbg_wvr5_arm, 120 dbg_wvr6_arm, 121 dbg_wvr7_arm, 122 dbg_wvr8_arm, 123 dbg_wvr9_arm, 124 dbg_wvr10_arm, 125 dbg_wvr11_arm, 126 dbg_wvr12_arm, 127 dbg_wvr13_arm, 128 dbg_wvr14_arm, 129 dbg_wvr15_arm, 130 dbg_wcr0_arm, 131 dbg_wcr1_arm, 132 dbg_wcr2_arm, 133 dbg_wcr3_arm, 134 dbg_wcr4_arm, 135 dbg_wcr5_arm, 136 dbg_wcr6_arm, 137 dbg_wcr7_arm, 138 dbg_wcr8_arm, 139 dbg_wcr9_arm, 140 dbg_wcr10_arm, 141 dbg_wcr11_arm, 142 dbg_wcr12_arm, 143 dbg_wcr13_arm, 144 dbg_wcr14_arm, 145 dbg_wcr15_arm, 146 147 k_num_registers_arm, 148 k_num_gpr_registers_arm = k_last_gpr_arm - k_first_gpr_arm + 1, 149 k_num_fpr_registers_arm = k_last_fpr_arm - k_first_fpr_arm + 1 150 }; 151 } 152 153 #endif // #ifndef lldb_arm64_register_enums_h 154