xref: /NextBSD/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrFormats.td (revision 84d351007654069f9643c8e4b4802a7f5f08ee42) 
1//=- MicroMips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes microMIPS32r6 instruction formats.
11//
12//===----------------------------------------------------------------------===//
13
14class MMR6Arch<string opstr> {
15  string Arch = "micromipsr6";
16  string BaseOpcode = opstr;
17}
18
19class POOL32A_BITSWAP_FM_MMR6<bits<6> funct> : MipsR6Inst {
20  bits<5> rd;
21  bits<5> rt;
22
23  bits<32> Inst;
24
25  let Inst{31-26} = 0b000000;
26  let Inst{25-21} = rt;
27  let Inst{20-16} = rd;
28  let Inst{15-12} = 0b0000;
29  let Inst{11-6} = funct;
30  let Inst{5-0} = 0b111100;
31}
32
33class CACHE_PREF_FM_MMR6<bits<6> opgroup, bits<4> funct> : MipsR6Inst {
34  bits<21> addr;
35  bits<5> hint;
36
37  bits<32> Inst;
38
39  let Inst{31-26} = opgroup;
40  let Inst{25-21} = hint;
41  let Inst{20-16} = addr{20-16};
42  let Inst{15-12} = funct;
43  let Inst{11-0}  = addr{11-0};
44}
45
46class ARITH_FM_MMR6<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
47  bits<5> rd;
48  bits<5> rt;
49  bits<5> rs;
50
51  bits<32> Inst;
52
53  let Inst{31-26} = 0;
54  let Inst{25-21} = rt;
55  let Inst{20-16} = rs;
56  let Inst{15-11} = rd;
57  let Inst{10}    = 0;
58  let Inst{9-0}   = funct;
59}
60
61class ADDI_FM_MMR6<string instr_asm, bits<6> op> : MMR6Arch<instr_asm> {
62  bits<5>  rt;
63  bits<5>  rs;
64  bits<16> imm16;
65
66  bits<32> Inst;
67
68  let Inst{31-26} = op;
69  let Inst{25-21} = rt;
70  let Inst{20-16} = rs;
71  let Inst{15-0}  = imm16;
72}
73
74class SIGN_EXTEND_FM_MMR6<string instr_asm, bits<10> funct>
75    : MMR6Arch<instr_asm> {
76  bits<5> rd;
77  bits<5> rt;
78
79  bits<32> Inst;
80
81  let Inst{31-26} = 0b000000;
82  let Inst{25-21} = rd;
83  let Inst{20-16} = rt;
84  let Inst{15-6}  = funct;
85  let Inst{5-0}   = 0b111100;
86}
87
88class PCREL19_FM_MMR6<bits<2> funct> : MipsR6Inst {
89  bits<5> rt;
90  bits<19> imm;
91
92  bits<32> Inst;
93
94  let Inst{31-26} = 0b011110;
95  let Inst{25-21} = rt;
96  let Inst{20-19} = funct;
97  let Inst{18-0}  = imm;
98}
99
100class PCREL16_FM_MMR6<bits<5> funct> : MipsR6Inst {
101  bits<5> rt;
102  bits<16> imm;
103
104  bits<32> Inst;
105
106  let Inst{31-26} = 0b011110;
107  let Inst{25-21} = rt;
108  let Inst{20-16} = funct;
109  let Inst{15-0}  = imm;
110}
111
112class POOL32A_FM_MMR6<bits<10> funct> : MipsR6Inst {
113  bits<5> rd;
114  bits<5> rs;
115  bits<5> rt;
116
117  bits<32> Inst;
118
119  let Inst{31-26} = 0b000000;
120  let Inst{25-21} = rt;
121  let Inst{20-16} = rs;
122  let Inst{15-11} = rd;
123  let Inst{10}    = 0;
124  let Inst{9-0}   = funct;
125}
126
127class POOL32A_2R_FM_MMR6<bits<10> funct> : MipsR6Inst {
128  bits<5> rs;
129  bits<5> rt;
130
131  bits<32> Inst;
132
133  let Inst{31-26} = 0b000000;
134  let Inst{25-21} = rt;
135  let Inst{20-16} = rs;
136  let Inst{15-6}  = funct;
137  let Inst{5-0}   = 0b111100;
138}
139
140class SPECIAL_2R_FM_MMR6<bits<6> funct> : MipsR6Inst {
141  bits<5> rs;
142  bits<5> rt;
143
144  bits<32> Inst;
145
146  let Inst{31-26} = 0b000000;
147  let Inst{25-21} = rs;
148  let Inst{20-16} = 0b00000;
149  let Inst{15-11} = rt;
150  let Inst{10-6}  = 0b00001;
151  let Inst{5-0}   = funct;
152}
153
154class POOL32A_ALIGN_FM_MMR6<bits<6> funct> : MipsR6Inst {
155  bits<5> rd;
156  bits<5> rs;
157  bits<5> rt;
158  bits<2> bp;
159
160  bits<32> Inst;
161
162  let Inst{31-26} = 0b000000;
163  let Inst{25-21} = rs;
164  let Inst{20-16} = rt;
165  let Inst{15-11} = rd;
166  let Inst{10-9}  = bp;
167  let Inst{8-6}   = 0b000;
168  let Inst{5-0}   = funct;
169}
170
171class AUI_FM_MMR6 : MipsR6Inst {
172  bits<5> rs;
173  bits<5> rt;
174  bits<16> imm;
175
176  bits<32> Inst;
177
178  let Inst{31-26} = 0b000100;
179  let Inst{25-21} = rt;
180  let Inst{20-16} = rs;
181  let Inst{15-0} = imm;
182}
183
184class POOL32A_LSA_FM<bits<6> funct> : MipsR6Inst {
185  bits<5> rd;
186  bits<5> rs;
187  bits<5> rt;
188  bits<2> imm2;
189
190  bits<32> Inst;
191
192  let Inst{31-26} = 0b000000;
193  let Inst{25-21} = rt;
194  let Inst{20-16} = rs;
195  let Inst{15-11} = rd;
196  let Inst{10-9}  = imm2;
197  let Inst{8-6}   = 0b000;
198  let Inst{5-0}   = funct;
199}
200
201class CMP_BRANCH_1R_RT_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
202  bits<5> rt;
203  bits<16> offset;
204
205  bits<32> Inst;
206
207  let Inst{31-26} = funct;
208  let Inst{25-21} = rt;
209  let Inst{20-16} = 0b00000;
210  let Inst{15-0}  = offset;
211}
212
213class CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<bits<6> funct> : MipsR6Inst {
214  bits<5> rt;
215  bits<16> offset;
216
217  bits<32> Inst;
218
219  let Inst{31-26} = funct;
220  let Inst{25-21} = rt;
221  let Inst{20-16} = rt;
222  let Inst{15-0}  = offset;
223}
224
225class ERET_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
226  bits<32> Inst;
227
228  let Inst{31-26} = 0x00;
229  let Inst{25-16} = 0x00;
230  let Inst{15-6}  = 0x3cd;
231  let Inst{5-0}   = 0x3c;
232}
233
234class ERETNC_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm> {
235  bits<32> Inst;
236
237  let Inst{31-26} = 0x00;
238  let Inst{25-17} = 0x00;
239  let Inst{16-16} = 0x01;
240  let Inst{15-6}  = 0x3cd;
241  let Inst{5-0}   = 0x3c;
242}
243
244class BREAK_MMR6_ENC<string instr_asm> : MMR6Arch<instr_asm> {
245  bits<10> code_1;
246  bits<10> code_2;
247  bits<32> Inst;
248  let Inst{31-26} = 0x0;
249  let Inst{25-16} = code_1;
250  let Inst{15-6}  = code_2;
251  let Inst{5-0}   = 0x07;
252}
253
254class BARRIER_MMR6_ENC<string instr_asm, bits<5> op> : MMR6Arch<instr_asm> {
255  bits<32> Inst;
256
257  let Inst{31-26} = 0x0;
258  let Inst{25-21} = 0x0;
259  let Inst{20-16} = 0x0;
260  let Inst{15-11} = op;
261  let Inst{10-6}  = 0x0;
262  let Inst{5-0}   = 0x0;
263}
264
265class EIDI_MMR6_ENC<string instr_asm, bits<10> funct> : MMR6Arch<instr_asm> {
266  bits<32> Inst;
267  bits<5> rt; // Actually rs but we're sharing code with the standard encodings which call it rt
268
269  let Inst{31-26} = 0x00;
270  let Inst{25-21} = 0x00;
271  let Inst{20-16} = rt;
272  let Inst{15-6}  = funct;
273  let Inst{5-0}   = 0x3c;
274}
275
276class SHIFT_MMR6_ENC<string instr_asm, bits<10> funct, bit rotate> : MMR6Arch<instr_asm> {
277  bits<5> rd;
278  bits<5> rt;
279  bits<5> shamt;
280
281  bits<32> Inst;
282
283  let Inst{31-26} = 0;
284  let Inst{25-21} = rd;
285  let Inst{20-16} = rt;
286  let Inst{15-11} = shamt;
287  let Inst{10}    = rotate;
288  let Inst{9-0}   = funct;
289}
290