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Searched refs:intel_ring_emit (Results 1 – 8 of 8) sorted by relevance

/freebsd-12-stable/sys/dev/drm2/i915/
Dintel_ringbuffer.c77 intel_ring_emit(ring, cmd); in gen2_render_ring_flush()
78 intel_ring_emit(ring, MI_NOOP); in gen2_render_ring_flush()
135 intel_ring_emit(ring, cmd); in gen4_render_ring_flush()
136 intel_ring_emit(ring, MI_NOOP); in gen4_render_ring_flush()
191 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); in intel_emit_post_sync_nonzero_flush()
192 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in intel_emit_post_sync_nonzero_flush()
194 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
195 intel_ring_emit(ring, 0); /* low dword */ in intel_emit_post_sync_nonzero_flush()
196 intel_ring_emit(ring, 0); /* high dword */ in intel_emit_post_sync_nonzero_flush()
197 intel_ring_emit(ring, MI_NOOP); in intel_emit_post_sync_nonzero_flush()
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Di915_gem_context.c361 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); in mi_set_context()
363 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
365 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
366 intel_ring_emit(ring, MI_SET_CONTEXT); in mi_set_context()
367 intel_ring_emit(ring, new_context->obj->gtt_offset | in mi_set_context()
373 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
376 intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE); in mi_set_context()
378 intel_ring_emit(ring, MI_NOOP); in mi_set_context()
Dintel_overlay.c255 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON); in intel_overlay_on()
256 intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE); in intel_overlay_on()
257 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_on()
258 intel_ring_emit(ring, MI_NOOP); in intel_overlay_on()
289 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_continue()
290 intel_ring_emit(ring, flip_addr); in intel_overlay_continue()
344 intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); in intel_overlay_off()
345 intel_ring_emit(ring, flip_addr); in intel_overlay_off()
346 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); in intel_overlay_off()
351 intel_ring_emit(ring, MI_NOOP); in intel_overlay_off()
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Di915_gem_execbuffer.c657 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in i915_gem_execbuffer_wait_for_flips()
658 intel_ring_emit(ring, MI_NOOP); in i915_gem_execbuffer_wait_for_flips()
825 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_reset_gen7_sol_offsets()
826 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i)); in i915_reset_gen7_sol_offsets()
827 intel_ring_emit(ring, 0); in i915_reset_gen7_sol_offsets()
1083 intel_ring_emit(ring, MI_NOOP); in i915_gem_do_execbuffer()
1084 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in i915_gem_do_execbuffer()
1085 intel_ring_emit(ring, INSTPM); in i915_gem_do_execbuffer()
1086 intel_ring_emit(ring, mask << 16 | mode); in i915_gem_do_execbuffer()
Dintel_ringbuffer.h206 static inline void intel_ring_emit(struct intel_ring_buffer *ring, in intel_ring_emit() function
Dintel_display.c7207 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen2_queue_flip()
7208 intel_ring_emit(ring, MI_NOOP); in intel_gen2_queue_flip()
7209 intel_ring_emit(ring, MI_DISPLAY_FLIP | in intel_gen2_queue_flip()
7211 intel_ring_emit(ring, fb->pitches[0]); in intel_gen2_queue_flip()
7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset); in intel_gen2_queue_flip()
7213 intel_ring_emit(ring, 0); /* aux display base address, unused */ in intel_gen2_queue_flip()
7248 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); in intel_gen3_queue_flip()
7249 intel_ring_emit(ring, MI_NOOP); in intel_gen3_queue_flip()
7250 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | in intel_gen3_queue_flip()
7252 intel_ring_emit(ring, fb->pitches[0]); in intel_gen3_queue_flip()
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Dintel_pm.c2811 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); in ironlake_enable_rc6()
2812 intel_ring_emit(ring, MI_SET_CONTEXT); in ironlake_enable_rc6()
2813 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | in ironlake_enable_rc6()
2818 intel_ring_emit(ring, MI_SUSPEND_FLUSH); in ironlake_enable_rc6()
2819 intel_ring_emit(ring, MI_NOOP); in ironlake_enable_rc6()
2820 intel_ring_emit(ring, MI_FLUSH); in ironlake_enable_rc6()
Di915_dma.c47 intel_ring_emit(LP_RING(dev_priv), x)