Lines Matching refs:intel_ring_emit
77 intel_ring_emit(ring, cmd); in gen2_render_ring_flush()
78 intel_ring_emit(ring, MI_NOOP); in gen2_render_ring_flush()
135 intel_ring_emit(ring, cmd); in gen4_render_ring_flush()
136 intel_ring_emit(ring, MI_NOOP); in gen4_render_ring_flush()
191 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); in intel_emit_post_sync_nonzero_flush()
192 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in intel_emit_post_sync_nonzero_flush()
194 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
195 intel_ring_emit(ring, 0); /* low dword */ in intel_emit_post_sync_nonzero_flush()
196 intel_ring_emit(ring, 0); /* high dword */ in intel_emit_post_sync_nonzero_flush()
197 intel_ring_emit(ring, MI_NOOP); in intel_emit_post_sync_nonzero_flush()
204 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); in intel_emit_post_sync_nonzero_flush()
205 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); in intel_emit_post_sync_nonzero_flush()
206 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ in intel_emit_post_sync_nonzero_flush()
207 intel_ring_emit(ring, 0); in intel_emit_post_sync_nonzero_flush()
208 intel_ring_emit(ring, 0); in intel_emit_post_sync_nonzero_flush()
209 intel_ring_emit(ring, MI_NOOP); in intel_emit_post_sync_nonzero_flush()
259 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); in gen6_render_ring_flush()
260 intel_ring_emit(ring, flags); in gen6_render_ring_flush()
261 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); in gen6_render_ring_flush()
262 intel_ring_emit(ring, 0); in gen6_render_ring_flush()
277 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); in gen7_render_ring_cs_stall_wa()
278 intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | in gen7_render_ring_cs_stall_wa()
280 intel_ring_emit(ring, 0); in gen7_render_ring_cs_stall_wa()
281 intel_ring_emit(ring, 0); in gen7_render_ring_cs_stall_wa()
336 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4)); in gen7_render_ring_flush()
337 intel_ring_emit(ring, flags); in gen7_render_ring_flush()
338 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); in gen7_render_ring_flush()
339 intel_ring_emit(ring, 0); in gen7_render_ring_flush()
585 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); in update_mboxes()
586 intel_ring_emit(ring, mmio_offset); in update_mboxes()
587 intel_ring_emit(ring, ring->outstanding_lazy_request); in update_mboxes()
615 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); in gen6_add_request()
616 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in gen6_add_request()
617 intel_ring_emit(ring, ring->outstanding_lazy_request); in gen6_add_request()
618 intel_ring_emit(ring, MI_USER_INTERRUPT); in gen6_add_request()
654 intel_ring_emit(waiter, in gen6_ring_sync()
656 intel_ring_emit(waiter, seqno); in gen6_ring_sync()
657 intel_ring_emit(waiter, 0); in gen6_ring_sync()
658 intel_ring_emit(waiter, MI_NOOP); in gen6_ring_sync()
666 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
668 intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
669 intel_ring_emit(ring__, 0); \
670 intel_ring_emit(ring__, 0); \
692 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | in pc_render_add_request()
695 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); in pc_render_add_request()
696 intel_ring_emit(ring, ring->outstanding_lazy_request); in pc_render_add_request()
697 intel_ring_emit(ring, 0); in pc_render_add_request()
710 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | in pc_render_add_request()
714 intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); in pc_render_add_request()
715 intel_ring_emit(ring, ring->outstanding_lazy_request); in pc_render_add_request()
716 intel_ring_emit(ring, 0); in pc_render_add_request()
893 intel_ring_emit(ring, MI_FLUSH); in bsd_ring_flush()
894 intel_ring_emit(ring, MI_NOOP); in bsd_ring_flush()
908 intel_ring_emit(ring, MI_STORE_DWORD_INDEX); in i9xx_add_request()
909 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); in i9xx_add_request()
910 intel_ring_emit(ring, ring->outstanding_lazy_request); in i9xx_add_request()
911 intel_ring_emit(ring, MI_USER_INTERRUPT); in i9xx_add_request()
979 intel_ring_emit(ring, in i965_dispatch_execbuffer()
983 intel_ring_emit(ring, offset); in i965_dispatch_execbuffer()
1003 intel_ring_emit(ring, MI_BATCH_BUFFER); in i830_dispatch_execbuffer()
1004 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); in i830_dispatch_execbuffer()
1005 intel_ring_emit(ring, offset + len - 8); in i830_dispatch_execbuffer()
1006 intel_ring_emit(ring, MI_NOOP); in i830_dispatch_execbuffer()
1021 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD | in i830_dispatch_execbuffer()
1024 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096); in i830_dispatch_execbuffer()
1025 intel_ring_emit(ring, 0); in i830_dispatch_execbuffer()
1026 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024); in i830_dispatch_execbuffer()
1027 intel_ring_emit(ring, cs_offset); in i830_dispatch_execbuffer()
1028 intel_ring_emit(ring, 0); in i830_dispatch_execbuffer()
1029 intel_ring_emit(ring, 4096); in i830_dispatch_execbuffer()
1030 intel_ring_emit(ring, offset); in i830_dispatch_execbuffer()
1031 intel_ring_emit(ring, MI_FLUSH); in i830_dispatch_execbuffer()
1034 intel_ring_emit(ring, MI_BATCH_BUFFER); in i830_dispatch_execbuffer()
1035 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); in i830_dispatch_execbuffer()
1036 intel_ring_emit(ring, cs_offset + len - 8); in i830_dispatch_execbuffer()
1054 intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT); in i915_dispatch_execbuffer()
1055 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE)); in i915_dispatch_execbuffer()
1521 intel_ring_emit(ring, cmd); in gen6_ring_flush()
1522 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); in gen6_ring_flush()
1523 intel_ring_emit(ring, 0); in gen6_ring_flush()
1524 intel_ring_emit(ring, MI_NOOP); in gen6_ring_flush()
1540 intel_ring_emit(ring, in hsw_ring_dispatch_execbuffer()
1544 intel_ring_emit(ring, offset); in hsw_ring_dispatch_execbuffer()
1561 intel_ring_emit(ring, in gen6_ring_dispatch_execbuffer()
1565 intel_ring_emit(ring, offset); in gen6_ring_dispatch_execbuffer()
1593 intel_ring_emit(ring, cmd); in blt_ring_flush()
1594 intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); in blt_ring_flush()
1595 intel_ring_emit(ring, 0); in blt_ring_flush()
1596 intel_ring_emit(ring, MI_NOOP); in blt_ring_flush()