Home
last modified time | relevance | path

Searched refs:idx_value (Results 1 – 6 of 6) sorted by relevance

/dragonfly/sys/dev/drm/radeon/
HDr200.c157 u32 idx_value; in r200_packet0_check() local
161 idx_value = radeon_get_ib_value(p, idx); in r200_packet0_check()
189 track->zb.offset = idx_value; in r200_packet0_check()
191 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
202 track->cb[0].offset = idx_value; in r200_packet0_check()
204 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
226 tmp = idx_value & ~(0x7 << 2); in r200_packet0_check()
230 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
273 track->textures[i].cube_info[face - 1].offset = idx_value; in r200_packet0_check()
274 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r200_packet0_check()
[all …]
HDr300.c631 u32 idx_value; in r300_packet0_check() local
635 idx_value = radeon_get_ib_value(p, idx); in r300_packet0_check()
667 track->cb[i].offset = idx_value; in r300_packet0_check()
669 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
680 track->zb.offset = idx_value; in r300_packet0_check()
682 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
710 ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ in r300_packet0_check()
711 ((idx_value & ~31) + (u32)reloc->gpu_offset); in r300_packet0_check()
720 tmp = idx_value + ((u32)reloc->gpu_offset); in r300_packet0_check()
730 track->vap_vf_cntl = idx_value; in r300_packet0_check()
[all …]
HDr100.c1320 u32 idx_value; in r100_packet3_load_vbpntr() local
1340 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1343 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1355 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1366 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1369 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1572 u32 idx_value; in r100_packet0_check() local
1577 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1606 track->zb.offset = idx_value; in r100_packet0_check()
1608 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
[all …]
HDr600_cs.c1636 u32 idx_value; in r600_packet3_check() local
1641 idx_value = radeon_get_ib_value(p, idx); in r600_packet3_check()
1674 (idx_value & 0xfffffff0) + in r600_packet3_check()
1715 idx_value + in r600_packet3_check()
1757 if (idx_value & 0x10) { in r600_packet3_check()
1772 } else if (idx_value & 0x100) { in r600_packet3_check()
1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; in r600_packet3_check()
1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET; in r600_packet3_check()
1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET; in r600_packet3_check()
2025 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET; in r600_packet3_check()
[all …]
HDevergreen_cs.c1780 u32 idx_value; in evergreen_packet3_check() local
1785 idx_value = radeon_get_ib_value(p, idx); in evergreen_packet3_check()
1818 (idx_value & 0xfffffff0) + in evergreen_packet3_check()
1864 idx_value + in evergreen_packet3_check()
1899 idx_value + in evergreen_packet3_check()
2010 if (idx_value != 1) { in evergreen_packet3_check()
2043 if (idx_value + size > track->indirect_draw_buffer_size) { in evergreen_packet3_check()
2045 idx_value, size, track->indirect_draw_buffer_size); in evergreen_packet3_check()
2077 ib[idx+0] = idx_value + (u32)(reloc->gpu_offset & 0xffffffff); in evergreen_packet3_check()
2090 if (idx_value & 0x10) { in evergreen_packet3_check()
[all …]
HDsi.c4470 u32 idx_value = ib[idx]; in si_vm_packet3_cp_dma_check() local
4474 start_reg = idx_value << 2; in si_vm_packet3_cp_dma_check()
4521 u32 idx_value = ib[idx]; in si_vm_packet3_gfx_check() local
4572 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4579 if ((idx_value & 0xf00) == 0) { in si_vm_packet3_gfx_check()
4581 if (idx_value & 0x10000) { in si_vm_packet3_gfx_check()
4594 if (idx_value & 0x100) { in si_vm_packet3_gfx_check()
4601 if (idx_value & 0x2) { in si_vm_packet3_gfx_check()
4608 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; in si_vm_packet3_gfx_check()
4639 u32 idx_value = ib[idx]; in si_vm_packet3_compute_check() local
[all …]