Lines Matching refs:idx_value
1320 u32 idx_value; in r100_packet3_load_vbpntr() local
1340 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1343 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1355 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1366 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1369 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1572 u32 idx_value; in r100_packet0_check() local
1577 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1606 track->zb.offset = idx_value; in r100_packet0_check()
1608 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1619 track->cb[0].offset = idx_value; in r100_packet0_check()
1621 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1640 tmp = idx_value & ~(0x7 << 2); in r100_packet0_check()
1644 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1661 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1662 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1679 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1680 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1697 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1698 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1703 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1721 tmp = idx_value & ~(0x7 << 16); in r100_packet0_check()
1725 ib[idx] = idx_value; in r100_packet0_check()
1727 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1731 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1735 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { in r100_packet0_check()
1753 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); in r100_packet0_check()
1756 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1761 switch (idx_value & 0xf) { in r100_packet0_check()
1786 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1790 uint32_t temp = idx_value >> 4; in r100_packet0_check()
1797 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1800 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1806 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1807 … track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1814 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1821 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1823 tmp = (idx_value >> 23) & 0x7; in r100_packet0_check()
1826 tmp = (idx_value >> 27) & 0x7; in r100_packet0_check()
1835 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { in r100_packet0_check()
1839 …track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDT… in r100_packet0_check()
1840 …track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HE… in r100_packet0_check()
1842 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) in r100_packet0_check()
1844 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { in r100_packet0_check()
1880 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1881 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1887 tmp = idx_value; in r100_packet0_check()