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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreInstrFormats.td13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
20 let AsmString = asmstr;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430InstrFormats.td55 string asmstr> : Instruction {
71 let AsmString = asmstr;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
[all …]
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrFormats.td14 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
26 let AsmString = asmstr;
68 class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
82 let AsmString = asmstr;
103 class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
105 : I<opcode, OOL, IOL, asmstr, itin> {
115 class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
116 : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
133 string asmstr>
134 : BForm<opcode, aa, lk, OOL, IOL, asmstr> {
[all …]
HDPPCInstrInfo.td752 string asmbase, string asmstr, InstrItinClass itin,
756 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
760 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
766 string asmbase, string asmstr, InstrItinClass itin,
771 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
775 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
781 string asmbase, string asmstr, InstrItinClass itin,
786 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
790 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
796 string asmbase, string asmstr, InstrItinClass itin,
[all …]
HDPPCInstrSPE.td15 class EVXForm_1<bits<11> xo, dag OOL, dag IOL, string asmstr,
16 InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> {
29 class EVXForm_2<bits<11> xo, dag OOL, dag IOL, string asmstr,
30 InstrItinClass itin> : EVXForm_1<xo, OOL, IOL, asmstr, itin> {
34 class EVXForm_3<bits<11> xo, dag OOL, dag IOL, string asmstr,
35 InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> {
49 class EVXForm_D<bits<11> xo, dag OOL, dag IOL, string asmstr,
50 InstrItinClass itin> : I<4, OOL, IOL, asmstr, itin> {
HDPPCInstrAltivec.td772 class VCMP<bits<10> xo, string asmstr, ValueType Ty>
773 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
776 class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
777 : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
HDPPCInstrVSX.td71 string asmbase, string asmstr, InstrItinClass itin,
75 !strconcat(asmbase, !strconcat(" ", asmstr)), itin,
79 !strconcat(asmbase, !strconcat(". ", asmstr)), itin,
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcInstrFormats.td10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
22 let AsmString = asmstr;
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
[all …]
HDSparcInstrVIS.td15 class VISInstFormat<bits<9> opfval, dag outs, dag ins, string asmstr,
17 : F3_3<0b10, 0b110110, opfval, outs, ins, asmstr, pattern>;
32 class VISInst0<bits<9> opfval, string asmstr>
33 : VISInstFormat<opfval, (outs), (ins), asmstr, []>;
HDSparcInstrInfo.td325 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
326 : InstSP<outs, ins, asmstr, pattern> {
580 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
581 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
595 class BranchSP<dag ins, string asmstr, list<dag> pattern>
596 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
599 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
600 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
650 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
651 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
[all …]
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrFormats.td75 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
82 let AsmString = asmstr;
196 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
198 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
201 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
203 : LDInst<outs, ins, asmstr, pattern, cstr>;
205 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
207 : LDInst<outs, ins, asmstr, pattern, cstr>;
211 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
213 : LDInst<outs, ins, asmstr, pattern, cstr>;
[all …]
HDHexagonInstrFormatsV4.td110 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
112 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon;
114 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
116 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
119 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
121 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
125 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
127 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
130 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
132 : NVInst<outs, ins, asmstr, pattern, cstr>;
[all …]
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips16InstrFormats.td36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
45 let AsmString = asmstr;
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
HDMips16InstrInfo.td40 class FI16_ins<bits<5> op, string asmstr, InstrItinClass itin>:
42 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>;
49 class FI816_ins_base<bits<3> _func, string asmstr,
51 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
54 class FI816_ins<bits<3> _func, string asmstr,
56 FI816_ins_base<_func, asmstr, "\t$imm # 16 bit inst", itin>;
58 class FI816_SP_ins<bits<3> _func, string asmstr,
60 FI816_ins_base<_func, asmstr, "\t$$sp, $imm # 16 bit inst", itin>;
67 class FRI16_ins_base<bits<5> op, string asmstr, string asmstr2,
70 !strconcat(asmstr, asmstr2), [], itin>;
[all …]
HDMipsInstrFormats.td72 class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
90 let AsmString = asmstr;
108 class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
110 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
134 class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
135 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
143 class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
145 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
167 class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
168 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
[all …]
HDMicroMipsInstrFormats.td9 class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
18 let AsmString = asmstr;
30 class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
32 MicroMipsInstBase<outs, ins, asmstr, pattern, itin, f>
HDMipsInstrInfo.td1053 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1055 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1057 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1059 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1500 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1501 FrmOther, asmstr>;
1546 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1547 FrmOther, asmstr>;
HDMips64InstrInfo.td355 class MFC2OP<string asmstr, RegisterOperand RO> :
357 !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFInstrFormats.td10 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
24 let AsmString = asmstr;
29 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
30 : InstBPF<outs, ins, asmstr, pattern> {
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrFormats.td14 class InstSystemZ<int size, dag outs, dag ins, string asmstr,
22 let AsmString = asmstr;
161 class InstRI<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
162 : InstSystemZ<4, outs, ins, asmstr, pattern> {
175 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
176 : InstSystemZ<6, outs, ins, asmstr, pattern> {
194 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
195 : InstSystemZ<6, outs, ins, asmstr, pattern> {
212 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
213 : InstSystemZ<6, outs, ins, asmstr, pattern> {
[all …]
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXVector.td18 class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
20 : NVPTXInst<outs, ins, asmstr, pattern> {
241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
244 asmstr.s,
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
251 asmstr.s,
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
258 asmstr.s,
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
[all …]
HDNVPTXInstrFormats.td23 class NVPTXInst<dag outs, dag ins, string asmstr, list<dag> pattern>
30 let AsmString = asmstr;
/NextBSD/contrib/llvm/tools/clang/lib/AST/
HDStmt.cpp692 StringLiteral *asmstr, unsigned numclobbers, in GCCAsmStmt() argument
695 numinputs, numclobbers), RParenLoc(rparenloc), AsmStr(asmstr) { in GCCAsmStmt()
717 StringRef asmstr, ArrayRef<StringRef> clobbers, in MSAsmStmt() argument
723 initialize(C, asmstr, asmtoks, constraints, exprs, clobbers); in MSAsmStmt()
735 void MSAsmStmt::initialize(const ASTContext &C, StringRef asmstr, in initialize() argument
747 AsmStr = copyIntoContext(C, asmstr); in initialize()
/NextBSD/contrib/llvm/tools/clang/include/clang/AST/
HDStmt.h1565 StringLiteral *asmstr, unsigned numclobbers,
1746 ArrayRef<Expr*> exprs, StringRef asmstr,
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600Instructions.td1485 class ILFormat<dag outs, dag ins, string asmstr, list<dag> pattern>
1492 let AsmString = !strconcat(asmstr, "\n");

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