Lines Matching refs:asmstr

18 class NVPTXVecInst<dag outs, dag ins, string asmstr, list<dag> pattern,
20   : NVPTXInst<outs, ins, asmstr, pattern> {
241 class VecBinaryOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass,
244                  asmstr.s,
248 class VecShiftOp<BinOpAsmString asmstr, SDNode OpNode, NVPTXRegClass regclass1,
251                  asmstr.s,
255 class VecUnaryOp<BinOpAsmString asmstr, PatFrag OpNode, NVPTXRegClass regclass,
258                  asmstr.s,
261 multiclass IntBinVOp<string asmstr, SDNode OpNode,
264   def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
266   def V4I32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "32")>, OpNode, V4I32Regs,
268   def V2I32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "32")>, OpNode, V2I32Regs,
270   def V4I16 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I16Regs,
272   def V2I16 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "16")>, OpNode, V2I16Regs,
274   def V4I8 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "16")>, OpNode, V4I8Regs,
276   def V2I8 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "16")>, OpNode, V2I8Regs,
280 multiclass FloatBinVOp<string asmstr, SDNode OpNode,
283   def V2F64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "f64")>, OpNode,
285   def V4F32_ftz : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
287   def V2F32_ftz : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "ftz.f32")>, OpNode,
289   def V4F32 : VecBinaryOp<V4AsmStr<!strconcat(asmstr, "f32")>, OpNode,
291   def V2F32 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "f32")>, OpNode,
295 multiclass IntUnaryVOp<string asmstr, PatFrag OpNode,
298   def V2I64 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "64")>, OpNode,
300   def V4I32 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "32")>, OpNode,
302   def V2I32 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "32")>, OpNode,
304   def V4I16 : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
306   def V2I16 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "16")>, OpNode,
308   def V4I8  : VecUnaryOp<V4UnaryStr<!strconcat(asmstr, "16")>, OpNode,
310   def V2I8  : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "16")>, OpNode,
354 class CVTtoVeci32<NVPTXRegClass inclass, NVPTXRegClass outclass, string asmstr,
356       NVPTXVecInst<(outs outclass:$d), (ins inclass:$s), asmstr, [], sInst>;
475 multiclass VMAD<string asmstr, NVPTXRegClass regclassv4,
481                       V4MADStr<asmstr>.s,
488                       V2MADStr<asmstr>.s,
495 multiclass VMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
499                       V2MADStr<asmstr>.s,
504 multiclass VFMADV2Only<string asmstr, NVPTXRegClass regclass, NVPTXInst sop=NOP,
508                       V2MADStr<asmstr>.s,
803 class Build_Vector2<string asmstr, NVPTXRegClass vclass, NVPTXRegClass sclass,
807                    !strconcat(asmstr, "\t${dst:vecfull}, {{$a1, $a2}};"),
810 class Build_Vector4<string asmstr, NVPTXRegClass vclass, NVPTXRegClass sclass,
814                !strconcat(asmstr, "\t${dst:vecfull}, {{$a1, $a2, $a3, $a4}};"),
845 class Vec_Move<string asmstr, NVPTXRegClass vclass, NVPTXInst sop=NOP>
847                    !strconcat(asmstr, "\t${dst:vecfull}, ${src:vecfull};"),
926 class Vec_Select<NVPTXRegClass vclass, string asmstr, NVPTXInst sop>
929                      asmstr,