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/freebsd-13-stable/sys/contrib/device-tree/Bindings/c6x/
HDclocks.txt1 C6X PLL Clock Controllers
10 - compatible: "ti,c64x+pll"
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
24 - ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
26 - ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
28 - ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
[all …]
/freebsd-13-stable/sys/mips/atheros/
HDar934x_chip.c92 uint32_t pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; in ar934x_chip_detect_sys_frequency() local
103 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL2_REG); in ar934x_chip_detect_sys_frequency()
104 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) { in ar934x_chip_detect_sys_frequency()
105 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
107 pll = ATH_READ_REG(AR934X_SRIF_CPU_DPLL1_REG); in ar934x_chip_detect_sys_frequency()
108 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) & in ar934x_chip_detect_sys_frequency()
110 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK; in ar934x_chip_detect_sys_frequency()
111 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
115 pll = ATH_READ_REG(AR934X_PLL_CPU_CONFIG_REG); in ar934x_chip_detect_sys_frequency()
116 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in ar934x_chip_detect_sys_frequency()
[all …]
HDqca955x_chip.c75 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca955x_chip_detect_sys_frequency() local
85 pll = ATH_READ_REG(QCA955X_PLL_CPU_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
86 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in qca955x_chip_detect_sys_frequency()
88 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in qca955x_chip_detect_sys_frequency()
90 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca955x_chip_detect_sys_frequency()
92 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca955x_chip_detect_sys_frequency()
99 pll = ATH_READ_REG(QCA955X_PLL_DDR_CONFIG_REG); in qca955x_chip_detect_sys_frequency()
100 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in qca955x_chip_detect_sys_frequency()
102 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in qca955x_chip_detect_sys_frequency()
104 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca955x_chip_detect_sys_frequency()
[all …]
HDqca953x_chip.c74 uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; in qca953x_chip_detect_sys_frequency() local
84 pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
85 out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in qca953x_chip_detect_sys_frequency()
87 ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in qca953x_chip_detect_sys_frequency()
89 nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) & in qca953x_chip_detect_sys_frequency()
91 frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in qca953x_chip_detect_sys_frequency()
98 pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG); in qca953x_chip_detect_sys_frequency()
99 out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in qca953x_chip_detect_sys_frequency()
101 ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in qca953x_chip_detect_sys_frequency()
103 nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) & in qca953x_chip_detect_sys_frequency()
[all …]
HDar91xx_chip.c68 uint32_t pll; in ar91xx_chip_detect_sys_frequency() local
74 pll = ATH_READ_REG(AR91XX_PLL_REG_CPU_CONFIG); in ar91xx_chip_detect_sys_frequency()
76 div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK); in ar91xx_chip_detect_sys_frequency()
80 div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1; in ar91xx_chip_detect_sys_frequency()
83 div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2; in ar91xx_chip_detect_sys_frequency()
117 ar91xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar91xx_chip_set_pll_ge() argument
123 AR91XX_PLL_REG_ETH0_INT_CLOCK, pll, in ar91xx_chip_set_pll_ge()
128 AR91XX_PLL_REG_ETH1_INT_CLOCK, pll, in ar91xx_chip_set_pll_ge()
132 printf("%s: invalid PLL set for arge unit: %d\n", in ar91xx_chip_set_pll_ge()
164 uint32_t pll; in ar91xx_chip_get_eth_pll() local
[all …]
HDar71xx_chip.c92 uint32_t pll; in ar71xx_chip_detect_sys_frequency() local
98 pll = ATH_READ_REG(AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_chip_detect_sys_frequency()
100 div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
103 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
106 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1; in ar71xx_chip_detect_sys_frequency()
109 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2; in ar71xx_chip_detect_sys_frequency()
233 ar71xx_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar71xx_chip_set_pll_ge() argument
239 AR71XX_PLL_ETH_INT0_CLK, pll, in ar71xx_chip_set_pll_ge()
244 AR71XX_PLL_ETH_INT1_CLK, pll, in ar71xx_chip_set_pll_ge()
248 printf("%s: invalid PLL set for arge unit: %d\n", in ar71xx_chip_set_pll_ge()
[all …]
HDar724x_chip.c70 uint32_t pll; in ar724x_chip_detect_sys_frequency() local
76 pll = ATH_READ_REG(AR724X_PLL_REG_CPU_CONFIG); in ar724x_chip_detect_sys_frequency()
78 div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK); in ar724x_chip_detect_sys_frequency()
81 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK); in ar724x_chip_detect_sys_frequency()
86 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1; in ar724x_chip_detect_sys_frequency()
89 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2; in ar724x_chip_detect_sys_frequency()
137 * XXX TODO: set the PLL for arge0 only on AR7242.
138 * The PLL/clock requirements are different.
144 ar724x_chip_set_pll_ge(int unit, int speed, uint32_t pll) in ar724x_chip_set_pll_ge() argument
155 printf("%s: invalid PLL set for arge unit: %d\n", in ar724x_chip_set_pll_ge()
/freebsd-13-stable/sys/contrib/device-tree/Bindings/clock/
HDkeystone-pll.txt3 Binding for keystone PLLs. The main PLL IP typically has a multiplier,
4 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
6 PLL is controlled by a PLL controller registers along with memory mapped
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
17 - reg - pll control0 and pll multipler registers
19 post-divider registers are applicable only for main pll clock
26 compatible = "ti,keystone,main-pll-clock";
35 compatible = "ti,keystone,pll-clock";
37 clock-output-names = "pa-pll-clk";
44 - compatible : shall be "ti,keystone,pll-mux-clock"
[all …]
HDqoriq-clock.txt5 multiple phase locked loops (PLL) to create a variety of frequencies
69 platform PLL.
87 4 platform pll n=pll/(n+1). For example, when n=1,
116 * "fsl,qoriq-core-pll-1.0" for core PLL clocks (v1.0)
117 * "fsl,qoriq-core-pll-2.0" for core PLL clocks (v2.0)
124 * "fsl,qoriq-platform-pll-1.0" for the platform PLL clock (v1.0)
125 * "fsl,qoriq-platform-pll-2.0" for the platform PLL clock (v2.0)
128 clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
129 For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
131 * 0 - equal to the PLL frequency
[all …]
Dqca,ath79-pll.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
6 - compatible: has to be "qca,<soctype>-pll" and one of the following
8 - "qca,ar7100-pll"
9 - "qca,ar7240-pll"
10 - "qca,ar9130-pll"
11 - "qca,ar9330-pll"
12 - "qca,ar9340-pll"
13 - "qca,qca9550-pll"
24 pll-controller@18050000 {
25 compatible = "qca,ar9132-pll", "qca,ar9130-pll";
HDvt8500.txt9 "via,vt8500-pll-clock" - for a VT8500/WM8505 PLL clock
10 "wm,wm8650-pll-clock" - for a WM8650 PLL clock
11 "wm,wm8750-pll-clock" - for a WM8750 PLL clock
12 "wm,wm8850-pll-clock" - for a WM8850 PLL clock
15 Required properties for PLL clocks:
16 - reg : shall be the control register offset from PMC base for the pll clock.
23 be a pll output.
61 compatible = "wm,wm8650-pll-clock";
HDclock-bindings.txt104 pll: pll@4c000 {
105 compatible = "vendor,some-pll-interface"
110 clock-output-names = "pll", "pll-switched";
114 * and the high frequency switched PLL output for register
120 clocks = <&osc 0>, <&pll 1>;
125 low-frequency reference clock, a PLL device to generate a higher frequency
129 * The PLL is both a clock provider and a clock consumer. It uses the clock
131 ("pll" and "pll-switched").
133 register clock connected to the PLL clock (the "pll-switched" signal)
153 clocks = <&osc 0>, <&pll 1>;
[all …]
Dbrcm,iproc-clocks.txt8 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
11 Required properties for a PLL and its leaf clocks:
14 Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
18 Have a value of <1> since there are more than 1 leaf clock of a given PLL
22 clock control registers required for the PLL
25 The input parent clock phandle for the PLL. For most iProc PLLs, this is an
89 PLL and leaf clock compatible strings for Cygnus are:
97 The following table defines the set of PLL/clock index and ID for Cygnus.
142 PLL and leaf clock compatible strings for Hurricane 2 are:
145 The following table defines the set of PLL/clock for Hurricane 2:
[all …]
Dsilabs,si5351.txt30 - silabs,pll-source: pair of (number, source) for each pll. Allows
31 to overwrite clock source of pll A (number=0) or B (number=1).
49 - silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
51 - silabs,pll-master: boolean, multisynth can change pll frequency.
52 - silabs,pll-reset: boolean, clock output can reset its pll.
83 silabs,pll-source = <0 0>, <1 0>;
98 silabs,pll-master;
114 pll-master;
Dsnps,hsdk-pll-clock.txt1 Binding for the HSDK Generic PLL clock
8 - compatible: should be "snps,hsdk-<name>-pll-clock"
9 "snps,hsdk-core-pll-clock"
10 "snps,hsdk-gp-pll-clock"
11 "snps,hsdk-hdmi-pll-clock"
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,hsdk-core-pll-clock";
Dsnps,pll-clock.txt1 Binding for the AXS10X Generic PLL clock
8 - compatible: should be "snps,axs10x-<name>-pll-clock"
9 "snps,axs10x-arc-pll-clock"
10 "snps,axs10x-pgu-pll-clock"
11 - reg: should always contain 2 pairs address - length: first for PLL config
13 - clocks: shall be the input parent clock phandle for the PLL.
24 compatible = "snps,axs10x-arc-pll-clock";
Dbaikal,bt1-ccu-pll.yaml5 $id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
8 title: Baikal-T1 Clock Control Unit PLL
52 with an interface wrapper (so called safe PLL' clocks switcher) to simplify
53 the PLL configuration procedure. The PLLs work as depicted on the next
71 divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
72 output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
73 the binding supports the PLL dividers configuration in accordance with a
81 The CCU PLL dts-node uses the common clock bindings with no custom
83 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
89 const: baikal,bt1-ccu-pll
[all …]
HDxgene.txt9 "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
10 "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
13 "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
14 "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
16 Required properties for SoC or PCP PLL clocks:
17 - reg : shall be the physical PLL register address for the pll clock.
21 - clock-output-names : shall be the name of the PLL referenced by derive
23 Optional properties for PLL clocks:
24 - clock-names : shall be the name of the PLL. If missing, use the device name.
32 Optional properties for PLL clocks:
Dsilabs,si5341.txt13 clocks. The chip contains a PLL that sources 5 (or 4) multisynth clocks, which
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
53 - silabs,pll-m-num, silabs,pll-m-den: Numerator and denominator for PLL
54 feedback divider. Must be such that the PLL output is in the valid range. For
57 If these are not specified, and the PLL is not yet programmed when the driver
58 probes, the PLL will be set to 14GHz.
113 silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
114 silabs,pll-m-den = <48>;
HDti-keystone-pllctrl.txt1 * Device tree bindings for Texas Instruments keystone pll controller
3 The main pll controller used to drive theC66x CorePacs, the switch fabric,
5 the NETCP modules) requires a PLL Controller to manage the various clock
12 - reg: contains offset/length value for pll controller
17 pllctrl: pll-controller@02310000 {
/freebsd-13-stable/sys/contrib/device-tree/Bindings/sound/
HDpcm512x.txt20 is absent the device will be configured to clock from BCLK. If pll-in
21 and pll-out are specified in addition to a clock, the device is
24 - pll-in, pll-out : gpio pins used to connect the pll using <1>
26 given pll-in pin and PLL output on the given pll-out pin. An
27 external connection from the pll-out pin to the SCLK pin is assumed.
50 pll-in = <3>;
51 pll-out = <6>;
/freebsd-13-stable/sys/contrib/device-tree/Bindings/usb/
Dnvidia,tegra124-xusb.txt49 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
50 - avdd-pll-erefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
51 - avdd-usb-ss-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
53 - hvdd-usb-ss-pll-e-supply: High-voltage PLLE power supply. Must supply 3.3 V.
59 - avdd-pll-utmip-supply: UTMI PLL power supply. Must supply 1.8 V.
60 - avdd-pll-uerefe-supply: PLLE reference PLL power supply. Must supply 1.05 V.
61 - dvdd-pex-pll-supply: PCIe/USB3 PLL power supply. Must supply 1.05 V.
62 - hvdd-pex-pll-e-supply: High-voltage PLLE power supply. Must supply 1.8 V.
127 avdd-pll-utmip-supply = <&vddio_1v8>;
128 avdd-pll-erefe-supply = <&avdd_1v05_run>;
[all …]
/freebsd-13-stable/sys/contrib/device-tree/Bindings/display/
Dallwinner,sun4i-a10-hdmi.yaml38 - description: The first video PLL
39 - description: The second video PLL
45 - description: The first video PLL
46 - description: The second video PLL
53 - const: pll-0
54 - const: pll-1
60 - const: pll-0
61 - const: pll-1
151 clock-names = "ahb", "mod", "pll-0", "pll-1";
/freebsd-13-stable/sys/arm/allwinner/clkng/
HDccu_a13.c139 CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll-ddr", 0x100, 0)
140 CCU_GATE(CLK_DRAM_CSI, "dram-csi", "pll-ddr", 0x100, 1)
141 CCU_GATE(CLK_DRAM_DE_FE, "dram-de-fe", "pll-ddr", 0x100, 25)
142 CCU_GATE(CLK_DRAM_DE_BE, "dram-de-be", "pll-ddr", 0x100, 26)
143 CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll-ddr", 0x100, 29)
144 CCU_GATE(CLK_DRAM_IEP, "dram-iep", "pll-ddr", 0x100, 31)
146 CCU_GATE(CLK_CODEC, "codec", "pll-audio", 0x140, 31)
155 .name = "pll-core",
169 * We only implement pll-audio for now
170 * For pll-audio-2/4/8 x we need a way to change the frequency
[all …]
/freebsd-13-stable/contrib/bc/tests/
HDall.sh48 pll=1
53 n) pll=0 ; set -e ;;
157 if [ "$pll" -ne 0 ]; then
167 if [ "$pll" -ne 0 ]; then
175 if [ "$pll" -ne 0 ]; then
185 if [ "$pll" -ne 0 ]; then
193 if [ "$pll" -ne 0 ]; then
207 if [ "$pll" -ne 0 ]; then
217 if [ "$pll" -ne 0 ]; then
224 if [ "$pll" -ne 0 ]; then

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