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Searched refs:uart_getreg (Results 1 – 17 of 17) sorted by relevance

/trueos/sys/mips/cavium/
HDuart_dev_oct16550.c88 iir = uart_getreg(bas, REG_IIR); in oct16550_clrint()
92 (void)uart_getreg(bas, REG_LSR); in oct16550_clrint()
94 (void)uart_getreg(bas, REG_DATA); in oct16550_clrint()
96 (void)uart_getreg(bas, REG_MSR); in oct16550_clrint()
98 (void) uart_getreg(bas, REG_USR); in oct16550_clrint()
100 iir = uart_getreg(bas, REG_IIR); in oct16550_clrint()
115 lcr = uart_getreg(bas, REG_LCR); in oct16550_delay()
118 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); in oct16550_delay()
171 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) in oct16550_drain()
189 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { in oct16550_drain()
[all …]
/trueos/sys/dev/uart/
HDuart_dev_ns8250.c74 iir = uart_getreg(bas, REG_IIR); in ns8250_clrint()
78 lsr = uart_getreg(bas, REG_LSR); in ns8250_clrint()
80 (void)uart_getreg(bas, REG_DATA); in ns8250_clrint()
82 (void)uart_getreg(bas, REG_DATA); in ns8250_clrint()
84 (void)uart_getreg(bas, REG_MSR); in ns8250_clrint()
86 iir = uart_getreg(bas, REG_IIR); in ns8250_clrint()
96 lcr = uart_getreg(bas, REG_LCR); in ns8250_delay()
99 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); in ns8250_delay()
148 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) in ns8250_drain()
166 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { in ns8250_drain()
[all …]
HDuart_dev_sab82532.c58 bgr = uart_getreg(bas, SAB_TCR); in sab82532_delay()
59 ccr2 = uart_getreg(bas, SAB_CCR2); in sab82532_delay()
108 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) in sab82532_flush()
114 while (uart_getreg(bas, SAB_STAR) & SAB_STAR_CEC) in sab82532_flush()
157 ccr2 = uart_getreg(bas, SAB_CCR2); in sab82532_param()
219 pvr = uart_getreg(bas, SAB_PVR); in sab82532_init()
259 uart_getreg(bas, SAB_ISR0); in sab82532_init()
260 uart_getreg(bas, SAB_ISR1); in sab82532_init()
275 pvr = uart_getreg(bas, SAB_PVR); in sab82532_term()
297 while ((uart_getreg(bas, SAB_STAR) & SAB_STAR_TEC) && --limit) in sab82532_putc()
[all …]
HDuart_dev_lpc.c65 iir = uart_getreg(bas, REG_IIR); in lpc_ns8250_clrint()
69 lsr = uart_getreg(bas, REG_LSR); in lpc_ns8250_clrint()
71 (void)uart_getreg(bas, REG_DATA); in lpc_ns8250_clrint()
73 (void)uart_getreg(bas, REG_DATA); in lpc_ns8250_clrint()
75 (void)uart_getreg(bas, REG_MSR); in lpc_ns8250_clrint()
77 iir = uart_getreg(bas, REG_IIR); in lpc_ns8250_clrint()
154 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) in lpc_ns8250_drain()
172 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { in lpc_ns8250_drain()
173 (void)uart_getreg(bas, REG_DATA); in lpc_ns8250_drain()
271 val = uart_getreg(bas, REG_IIR); in lpc_ns8250_probe()
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HDuart_dev_msm.c238 if (!(uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXEMT)) { in msm_putc()
239 while ((uart_getreg(bas, UART_DM_ISR) & UART_DM_TX_READY) == 0 in msm_putc()
247 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_TXRDY) == 0) in msm_putc()
259 return ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) == in msm_rxready()
271 while ((uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) != in msm_getc()
276 if (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_UART_OVERRUN) in msm_getc()
280 c = uart_getreg(bas, UART_DM_RF(0)); in msm_getc()
412 while (uart_getreg(bas, UART_DM_SR) & UART_DM_SR_RXRDY) { in msm_bus_receive()
420 c = uart_getreg(bas, UART_DM_RF(0)); in msm_bus_receive()
HDuart_dev_z8530.c69 return (uart_getreg(bas, REG_CTRL)); in uart_getmreg()
231 while (!(uart_getreg(bas, REG_CTRL) & BES_TXE)) in z8530_putc()
241 return ((uart_getreg(bas, REG_CTRL) & BES_RXA) != 0 ? 1 : 0); in z8530_rxready()
251 while (!(uart_getreg(bas, REG_CTRL) & BES_RXA)) { in z8530_getc()
257 c = uart_getreg(bas, REG_DATA); in z8530_getc()
544 xc = uart_getreg(bas, REG_DATA); in z8530_bus_receive()
562 (void)uart_getreg(bas, REG_DATA); in z8530_bus_receive()
HDuart.h48 #define uart_getreg(bas, reg) \ macro
HDuart_dev_ti8250.c107 while (uart_getreg(&sc->sc_bas, SYSS_REG) & SYSS_STATUS_RESETDONE) in ti8250_bus_probe()
/trueos/sys/mips/adm5120/
HDuart_dev_adm5120.c97 while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL) in adm5120_uart_putc()
100 while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY) in adm5120_uart_putc()
108 if (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) in adm5120_uart_rxready()
121 while (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) { in adm5120_uart_getc()
127 c = uart_getreg(bas, UART_DR_REG); in adm5120_uart_getc()
196 cr = uart_getreg(&sc->sc_bas, UART_CR_REG); in adm5120_uart_disable_txintr()
209 cr = uart_getreg(&sc->sc_bas, UART_CR_REG); in adm5120_uart_enable_txintr()
233 uart_getreg(bas, UART_LCR_H_REG) | UART_LCR_H_FEN); in adm5120_uart_bus_attach()
267 bes = uart_getreg(&sc->sc_bas, UART_FR_REG); in adm5120_uart_bus_getsig()
292 divisor = uart_getreg(bas, UART_LCR_M_REG); in adm5120_uart_bus_ioctl()
[all …]
/trueos/sys/arm/freescale/vybrid/
HDvf_uart.c157 while (!(uart_getreg(bas, UART_S1) & UART_S1_TDRE)) in vf_uart_putc()
168 usr1 = uart_getreg(bas, UART_S1); in vf_uart_rxready()
183 while (!(uart_getreg(bas, UART_S1) & UART_S1_RDRF)) in vf_uart_getc()
186 c = uart_getreg(bas, UART_D); in vf_uart_getc()
219 reg = uart_getreg(bas, UART_C2); in uart_reinit()
228 reg = uart_getreg(bas, UART_BDH); in uart_reinit()
236 reg = uart_getreg(bas, UART_C4); in uart_reinit()
241 reg = uart_getreg(bas, UART_C2); in uart_reinit()
302 reg = uart_getreg(bas, UART_C2); in vf_uart_bus_attach()
377 usr1 = uart_getreg(bas, UART_S1); in vf_uart_bus_ipend()
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/trueos/sys/mips/rt305x/
HDuart_dev_rt305x.c141 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE)); in rt305x_uart_putc()
144 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_THRE)); in rt305x_uart_putc()
151 if (uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR) in rt305x_uart_rxready()
167 while (!(uart_getreg(bas, UART_LSR_REG) & UART_LSR_DR)) { in rt305x_uart_getc()
173 c = uart_getreg(bas, UART_RX_REG); in rt305x_uart_getc()
243 cr = uart_getreg(bas, UART_IER_REG); in rt305x_uart_disable_txintr()
258 cr = uart_getreg(bas, UART_IER_REG); in rt305x_uart_enable_txintr()
283 uart_getreg(bas, UART_FCR_REG) | in rt305x_uart_bus_attach()
305 uint32_t fcr = uart_getreg(bas, UART_FCR_REG); in rt305x_uart_bus_flush()
329 bes = uart_getreg(&sc->sc_bas, UART_MSR_REG); in rt305x_uart_bus_getsig()
[all …]
HDuart_dev_rt305x.h36 #undef uart_getreg
38 #define uart_getreg(bas, reg) \ macro
/trueos/sys/arm/allwinner/
HDconsole.c57 uart_getreg(uint32_t *bas) in uart_getreg() function
71 while ((uart_getreg((uint32_t *)(A10_UART_BASE + in ub_getc()
75 return (uart_getreg((uint32_t *)A10_UART_BASE) & 0xff); in ub_getc()
84 while ((uart_getreg((uint32_t *)(A10_UART_BASE + in ub_putc()
/trueos/sys/mips/atheros/
HDuart_dev_ar933x.c457 lcr = uart_getreg(bas, REG_LCR); in ar933x_bus_ioctl()
466 lcr = uart_getreg(bas, REG_LCR); in ar933x_bus_ioctl()
470 efr = uart_getreg(bas, REG_EFR); in ar933x_bus_ioctl()
481 lcr = uart_getreg(bas, REG_LCR); in ar933x_bus_ioctl()
485 efr = uart_getreg(bas, REG_EFR); in ar933x_bus_ioctl()
496 lcr = uart_getreg(bas, REG_LCR); in ar933x_bus_ioctl()
499 divisor = uart_getreg(bas, REG_DLL) | in ar933x_bus_ioctl()
500 (uart_getreg(bas, REG_DLH) << 8); in ar933x_bus_ioctl()
/trueos/sys/boot/arm/ixp425/boot2/
HDixp425_board.c60 static u_int8_t uart_getreg(u_int8_t *, int);
140 uart_getreg(u_int8_t *bas, int off) in uart_getreg() function
159 while ((uart_getreg(ubase, REG_LSR) & LSR_RXRDY) == 0 && --limit) in getc()
162 if ((uart_getreg(ubase, REG_LSR) & LSR_RXRDY) == LSR_RXRDY) in getc()
163 c = uart_getreg(ubase, REG_DATA); in getc()
175 while ((uart_getreg(ubase, REG_LSR) & LSR_THRE) == 0 && --limit) in putchar()
180 while ((uart_getreg(ubase, REG_LSR) & LSR_TEMT) == 0 && --limit) in putchar()
/trueos/sys/arm/samsung/s3c2xx0/
HDuart_dev_s3c2410.c194 return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == in s3c2410_rxready()
304 uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); in s3c2410_bus_receive()
/trueos/sys/arm/samsung/exynos/
HDexynos_uart.c191 return ((uart_getreg(bas, SSCOM_UTRSTAT) & UTRSTAT_RXREADY) == in exynos4210_rxready()
295 uart_rx_put(sc, uart_getreg(&sc->sc_bas, SSCOM_URXH)); in exynos4210_bus_receive()