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Searched refs:pll_max_in (Results 1 – 7 of 7) sorted by relevance

/trueos/sys/arm/at91/
HDat91sam9260.c175 clk->pll_max_in = SAM9260_PLL_A_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
195 clk->pll_max_in = SAM9260_PLL_B_MAX_IN_FREQ; /* 5 MHz */ in at91_clock_init()
196 clk->pll_max_in = 2999999; /* ~3 MHz */ in at91_clock_init()
HDat91sam9g20.c150 clk->pll_max_in = SAM9G20_PLL_A_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
162 clk->pll_max_in = SAM9G20_PLL_B_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
HDat91sam9x5.c154 clk->pll_max_in = SAM9X25_PLL_A_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
166 clk->pll_max_in = SAM9X25_PLL_B_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
HDat91rm9200.c177 clk->pll_max_in = RM9200_PLL_A_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
189 clk->pll_max_in = RM9200_PLL_B_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
HDat91_pmcvar.h46 uint32_t pll_max_in; member
HDat91sam9g45.c149 clk->pll_max_in = SAM9G45_PLL_A_MAX_IN_FREQ; /* 32 MHz */ in at91_clock_init()
HDat91_pmc.c445 if (input > clk->pll_max_in) in at91_pmc_pll_calc()