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/trueos/sys/arm/samsung/exynos/
HDexynos5_common.h29 #define READ4(_sc, _reg) \ argument
30 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
31 #define WRITE4(_sc, _reg, _val) \ argument
32 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
33 #define READ2(_sc, _reg) \ argument
34 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
37 #define READ1(_sc, _reg) \ argument
38 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
[all …]
/trueos/sys/arm/freescale/vybrid/
HDvf_common.h29 #define READ4(_sc, _reg) \ argument
30 bus_space_read_4(_sc->bst, _sc->bsh, _reg)
31 #define WRITE4(_sc, _reg, _val) \ argument
32 bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
33 #define READ2(_sc, _reg) \ argument
34 bus_space_read_2(_sc->bst, _sc->bsh, _reg)
35 #define WRITE2(_sc, _reg, _val) \ argument
36 bus_space_write_2(_sc->bst, _sc->bsh, _reg, _val)
37 #define READ1(_sc, _reg) \ argument
38 bus_space_read_1(_sc->bst, _sc->bsh, _reg)
[all …]
HDvf_edma.h111 #define TCD_READ4(_sc, _reg) \ argument
112 bus_space_read_4(_sc->bst_tcd, _sc->bsh_tcd, _reg)
113 #define TCD_WRITE4(_sc, _reg, _val) \ argument
114 bus_space_write_4(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
115 #define TCD_READ2(_sc, _reg) \ argument
116 bus_space_read_2(_sc->bst_tcd, _sc->bsh_tcd, _reg)
117 #define TCD_WRITE2(_sc, _reg, _val) \ argument
118 bus_space_write_2(_sc->bst_tcd, _sc->bsh_tcd, _reg, _val)
119 #define TCD_READ1(_sc, _reg) \ argument
120 bus_space_read_1(_sc->bst_tcd, _sc->bsh_tcd, _reg)
[all …]
/trueos/sys/net/
HDif_bridgevar.h272 #define BRIDGE_LOCK_INIT(_sc) do { \ argument
273 mtx_init(&(_sc)->sc_mtx, "if_bridge", NULL, MTX_DEF); \
274 cv_init(&(_sc)->sc_cv, "if_bridge_cv"); \
276 #define BRIDGE_LOCK_DESTROY(_sc) do { \ argument
277 mtx_destroy(&(_sc)->sc_mtx); \
278 cv_destroy(&(_sc)->sc_cv); \
280 #define BRIDGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
281 #define BRIDGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
282 #define BRIDGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
283 #define BRIDGE_LOCK2REF(_sc, _err) do { \ argument
[all …]
HDif_lagg.h261 #define LAGG_LOCK_INIT(_sc) rm_init(&(_sc)->sc_mtx, "if_lagg rmlock") argument
262 #define LAGG_LOCK_DESTROY(_sc) rm_destroy(&(_sc)->sc_mtx) argument
263 #define LAGG_RLOCK(_sc, _p) rm_rlock(&(_sc)->sc_mtx, (_p)) argument
264 #define LAGG_WLOCK(_sc) rm_wlock(&(_sc)->sc_mtx) argument
265 #define LAGG_RUNLOCK(_sc, _p) rm_runlock(&(_sc)->sc_mtx, (_p)) argument
266 #define LAGG_WUNLOCK(_sc) rm_wunlock(&(_sc)->sc_mtx) argument
267 #define LAGG_RLOCK_ASSERT(_sc) rm_assert(&(_sc)->sc_mtx, RA_RLOCKED) argument
268 #define LAGG_WLOCK_ASSERT(_sc) rm_assert(&(_sc)->sc_mtx, RA_WLOCKED) argument
270 #define LAGG_CALLOUT_LOCK_INIT(_sc) \ argument
271 mtx_init(&(_sc)->sc_call_mtx, "if_lagg callout mutex", NULL,\
[all …]
/trueos/sys/dev/ath/
HDif_ath_rx.h38 #define ath_stoprecv(_sc, _dodelay) \ argument
39 (_sc)->sc_rx.recv_stop((_sc), (_dodelay))
40 #define ath_startrecv(_sc) \ argument
41 (_sc)->sc_rx.recv_start((_sc))
42 #define ath_rx_flush(_sc) \ argument
43 (_sc)->sc_rx.recv_flush((_sc))
44 #define ath_rxbuf_init(_sc, _bf) \ argument
45 (_sc)->sc_rx.recv_rxbuf_init((_sc), (_bf))
46 #define ath_rxdma_setup(_sc) \ argument
47 (_sc)->sc_rx.recv_setup(_sc)
[all …]
HDif_athvar.h378 #define ATH_TXQ_LOCK_INIT(_sc, _tq) do { \ argument
380 device_get_nameunit((_sc)->sc_dev), (_tq)->axq_qnum); \
869 #define ATH_LOCK_INIT(_sc) \ argument
870 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
872 #define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
873 #define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
874 #define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
875 #define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) argument
876 #define ATH_UNLOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED) argument
882 #define ATH_TX_LOCK_INIT(_sc) do {\ argument
[all …]
HDif_ath_tx.h156 #define ath_txdma_setup(_sc) \ argument
157 (_sc)->sc_tx.xmit_setup(_sc)
158 #define ath_txdma_teardown(_sc) \ argument
159 (_sc)->sc_tx.xmit_teardown(_sc)
160 #define ath_txq_restart_dma(_sc, _txq) \ argument
161 (_sc)->sc_tx.xmit_dma_restart((_sc), (_txq))
162 #define ath_tx_handoff(_sc, _txq, _bf) \ argument
163 (_sc)->sc_tx.xmit_handoff((_sc), (_txq), (_bf))
164 #define ath_draintxq(_sc, _rtype) \ argument
165 (_sc)->sc_tx.xmit_drain((_sc), (_rtype))
/trueos/sys/arm/ti/
HDti_adcvar.h34 #define ADC_READ4(_sc, reg) bus_read_4((_sc)->sc_mem_res, reg) argument
35 #define ADC_WRITE4(_sc, reg, value) \ argument
36 bus_write_4((_sc)->sc_mem_res, reg, value)
57 #define TI_ADC_LOCK(_sc) \ argument
58 mtx_lock(&(_sc)->sc_mtx)
59 #define TI_ADC_UNLOCK(_sc) \ argument
60 mtx_unlock(&(_sc)->sc_mtx)
61 #define TI_ADC_LOCK_INIT(_sc) \ argument
62 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
64 #define TI_ADC_LOCK_DESTROY(_sc) \ argument
[all …]
/trueos/sys/dev/e1000/
HDif_em.h484 #define EM_CORE_LOCK_INIT(_sc, _name) \ argument
485 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
486 #define EM_TX_LOCK_INIT(_sc, _name) \ argument
487 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
488 #define EM_RX_LOCK_INIT(_sc, _name) \ argument
489 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
490 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) argument
491 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) argument
492 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) argument
493 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) argument
[all …]
HDif_lem.h478 #define EM_CORE_LOCK_INIT(_sc, _name) \ argument
479 mtx_init(&(_sc)->core_mtx, _name, "EM Core Lock", MTX_DEF)
480 #define EM_TX_LOCK_INIT(_sc, _name) \ argument
481 mtx_init(&(_sc)->tx_mtx, _name, "EM TX Lock", MTX_DEF)
482 #define EM_RX_LOCK_INIT(_sc, _name) \ argument
483 mtx_init(&(_sc)->rx_mtx, _name, "EM RX Lock", MTX_DEF)
484 #define EM_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) argument
485 #define EM_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) argument
486 #define EM_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) argument
487 #define EM_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) argument
[all …]
HDif_igb.h530 #define IGB_CORE_LOCK_INIT(_sc, _name) \ argument
531 mtx_init(&(_sc)->core_mtx, _name, "IGB Core Lock", MTX_DEF)
532 #define IGB_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) argument
533 #define IGB_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) argument
534 #define IGB_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) argument
535 #define IGB_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) argument
537 #define IGB_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) argument
538 #define IGB_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) argument
539 #define IGB_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) argument
540 #define IGB_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) argument
[all …]
/trueos/sys/dev/mwl/
HDif_mwlvar.h130 #define MWL_TXQ_LOCK_INIT(_sc, _tq) do { \ argument
132 device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \
154 #define MWL_JUMBO_OFFSET(_sc, _data) \ argument
155 (((const uint8_t *)(_data)) - (const uint8_t *)((_sc)->sc_rxmem))
156 #define MWL_JUMBO_DMA_ADDR(_sc, _data) \ argument
157 ((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data))
338 #define MWL_LOCK_INIT(_sc) \ argument
339 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
341 #define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) argument
342 #define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
[all …]
/trueos/sys/dev/age/
HDif_agevar.h237 #define CSR_WRITE_4(_sc, reg, val) \ argument
238 bus_write_4((_sc)->age_res[0], (reg), (val))
239 #define CSR_WRITE_2(_sc, reg, val) \ argument
240 bus_write_2((_sc)->age_res[0], (reg), (val))
241 #define CSR_READ_2(_sc, reg) \ argument
242 bus_read_2((_sc)->age_res[0], (reg))
243 #define CSR_READ_4(_sc, reg) \ argument
244 bus_read_4((_sc)->age_res[0], (reg))
246 #define AGE_LOCK(_sc) mtx_lock(&(_sc)->age_mtx) argument
247 #define AGE_UNLOCK(_sc) mtx_unlock(&(_sc)->age_mtx) argument
[all …]
/trueos/sys/dev/scd/
HDscdvar.h55 #define SCD_LOCK(_sc) splx(&(_sc)->mtx argument
56 #define SCD_UNLOCK(_sc) splx(&(_sc)->mtx argument
58 #define SCD_READ(_sc, _reg) \ argument
59 bus_space_read_1(_sc->port_bst, _sc->port_bsh, _reg)
60 #define SCD_READ_MULTI(_sc, _reg, _addr, _count) \ argument
61 bus_space_read_multi_1(_sc->port_bst, _sc->port_bsh, _reg, _addr, _count)
62 #define SCD_WRITE(_sc, _reg, _val) \ argument
63 bus_space_write_1(_sc->port_bst, _sc->port_bsh, _reg, _val)
/trueos/sys/dev/virtio/scsi/
HDvirtio_scsivar.h144 #define VTSCSI_MTX(_sc) &(_sc)->vtscsi_mtx argument
145 #define VTSCSI_LOCK_INIT(_sc, _name) mtx_init(VTSCSI_MTX(_sc), _name, \ argument
147 #define VTSCSI_LOCK(_sc) mtx_lock(VTSCSI_MTX(_sc)) argument
148 #define VTSCSI_UNLOCK(_sc) mtx_unlock(VTSCSI_MTX(_sc)) argument
149 #define VTSCSI_LOCK_OWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_OWNED) argument
150 #define VTSCSI_LOCK_NOTOWNED(_sc) mtx_assert(VTSCSI_MTX(_sc), MA_NOTOWNED) argument
151 #define VTSCSI_LOCK_DESTROY(_sc) mtx_destroy(VTSCSI_MTX(_sc)) argument
172 #define vtscsi_dprintf(_sc, _level, _msg, _args ...) do { \ argument
173 if ((_sc)->vtscsi_debug & (_level)) \
174 device_printf((_sc)->vtscsi_dev, "%s: "_msg, \
/trueos/sys/dev/gpio/
HDgpiobusvar.h52 #define GPIOBUS_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
53 #define GPIOBUS_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
54 #define GPIOBUS_LOCK_INIT(_sc) mtx_init(&_sc->sc_mtx, \ argument
55 device_get_nameunit(_sc->sc_dev), "gpiobus", MTX_DEF)
56 #define GPIOBUS_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) argument
57 #define GPIOBUS_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) argument
58 #define GPIOBUS_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) argument
/trueos/sys/dev/alc/
HDif_alcvar.h258 #define CSR_WRITE_4(_sc, reg, val) \ argument
259 bus_write_4((_sc)->alc_res[0], (reg), (val))
260 #define CSR_WRITE_2(_sc, reg, val) \ argument
261 bus_write_2((_sc)->alc_res[0], (reg), (val))
262 #define CSR_WRITE_1(_sc, reg, val) \ argument
263 bus_write_1((_sc)->alc_res[0], (reg), (val))
264 #define CSR_READ_2(_sc, reg) \ argument
265 bus_read_2((_sc)->alc_res[0], (reg))
266 #define CSR_READ_4(_sc, reg) \ argument
267 bus_read_4((_sc)->alc_res[0], (reg))
[all …]
/trueos/sys/dev/stge/
HDif_stgereg.h88 #define CSR_WRITE_4(_sc, reg, val) \ argument
89 bus_write_4((_sc)->sc_res[0], (reg), (val))
90 #define CSR_WRITE_2(_sc, reg, val) \ argument
91 bus_write_2((_sc)->sc_res[0], (reg), (val))
92 #define CSR_WRITE_1(_sc, reg, val) \ argument
93 bus_write_1((_sc)->sc_res[0], (reg), (val))
95 #define CSR_READ_4(_sc, reg) \ argument
96 bus_read_4((_sc)->sc_res[0], (reg))
97 #define CSR_READ_2(_sc, reg) \ argument
98 bus_read_2((_sc)->sc_res[0], (reg))
[all …]
/trueos/sys/dev/sn/
HDif_snvar.h73 #define SN_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) argument
74 #define SN_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) argument
75 #define SN_LOCK_INIT(_sc) \ argument
76 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->dev), \
78 #define SN_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx); argument
79 #define SN_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED); argument
80 #define SN_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED); argument
/trueos/sys/arm/broadcom/bcm2835/
HDbcm2835_spivar.h62 #define BCM_SPI_WRITE(_sc, _off, _val) \ argument
63 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
64 #define BCM_SPI_READ(_sc, _off) \ argument
65 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
67 #define BCM_SPI_LOCK(_sc) \ argument
68 mtx_lock(&(_sc)->sc_mtx)
69 #define BCM_SPI_UNLOCK(_sc) \ argument
70 mtx_unlock(&(_sc)->sc_mtx)
HDbcm2835_bscvar.h60 #define BCM_BSC_WRITE(_sc, _off, _val) \ argument
61 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
62 #define BCM_BSC_READ(_sc, _off) \ argument
63 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
65 #define BCM_BSC_LOCK(_sc) \ argument
66 mtx_lock(&(_sc)->sc_mtx)
67 #define BCM_BSC_UNLOCK(_sc) \ argument
68 mtx_unlock(&(_sc)->sc_mtx)
/trueos/sys/dev/virtio/network/
HDif_vtnetvar.h337 #define VTNET_NEEDED_RX_MBUFS(_sc, _clsize) \ argument
338 ((_sc)->vtnet_flags & VTNET_FLAG_LRO_NOMRG) == 0 ? 1 : \
342 #define VTNET_CORE_MTX(_sc) &(_sc)->vtnet_mtx argument
343 #define VTNET_CORE_LOCK(_sc) mtx_lock(VTNET_CORE_MTX((_sc))) argument
344 #define VTNET_CORE_UNLOCK(_sc) mtx_unlock(VTNET_CORE_MTX((_sc))) argument
345 #define VTNET_CORE_LOCK_DESTROY(_sc) mtx_destroy(VTNET_CORE_MTX((_sc))) argument
346 #define VTNET_CORE_LOCK_ASSERT(_sc) \ argument
347 mtx_assert(VTNET_CORE_MTX((_sc)), MA_OWNED)
348 #define VTNET_CORE_LOCK_ASSERT_NOTOWNED(_sc) \ argument
349 mtx_assert(VTNET_CORE_MTX((_sc)), MA_NOTOWNED)
[all …]
/trueos/sys/dev/ixl/
HDixl_pf.h89 #define IXL_PF_LOCK_INIT(_sc, _name) \ argument
90 mtx_init(&(_sc)->pf_mtx, _name, "IXL PF Lock", MTX_DEF)
91 #define IXL_PF_LOCK(_sc) mtx_lock(&(_sc)->pf_mtx) argument
92 #define IXL_PF_UNLOCK(_sc) mtx_unlock(&(_sc)->pf_mtx) argument
93 #define IXL_PF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->pf_mtx) argument
94 #define IXL_PF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pf_mtx, MA_OWNED) argument
/trueos/sys/dev/etherswitch/ip17x/
HDip17x_var.h77 #define IP17X_IS_SWITCH(_sc, _type) \ argument
78 (!!((_sc)->sc_switchtype == IP17X_SWITCH_ ## _type))
80 #define IP17X_LOCK(_sc) \ argument
81 mtx_lock(&(_sc)->sc_mtx)
82 #define IP17X_UNLOCK(_sc) \ argument
83 mtx_unlock(&(_sc)->sc_mtx)
84 #define IP17X_LOCK_ASSERT(_sc, _what) \ argument
85 mtx_assert(&(_sc)->sc_mtx, (_what))
86 #define IP17X_TRYLOCK(_sc) \ argument
87 mtx_trylock(&(_sc)->sc_mtx)

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