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Searched refs:WR4 (Results 1 – 25 of 30) sorted by relevance

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/trueos/sys/arm/at91/
HDat91_spi.c84 WR4(struct at91_spi_softc *sc, bus_size_t off, uint32_t val) in WR4() function
147 WR4(sc, SPI_CR, SPI_CR_SWRST); in at91_spi_attach()
149 WR4(sc, SPI_CR, SPI_CR_SWRST); in at91_spi_attach()
150 WR4(sc, SPI_IDR, 0xffffffff); in at91_spi_attach()
152 WR4(sc, SPI_MR, (0xf << 24) | SPI_MR_MSTR | SPI_MR_MODFDIS | in at91_spi_attach()
172 WR4(sc, SPI_CSR0, csr); in at91_spi_attach()
173 WR4(sc, SPI_CSR1, csr); in at91_spi_attach()
174 WR4(sc, SPI_CSR2, csr); in at91_spi_attach()
175 WR4(sc, SPI_CSR3, csr); in at91_spi_attach()
177 WR4(sc, SPI_CR, SPI_CR_SPIEN); in at91_spi_attach()
[all …]
HDuart_dev_at91usart.c86 #define WR4(bas, reg, value) \ macro
199 WR4(bas, USART_MR, mr); in at91_usart_param()
205 WR4(bas, USART_BRGR, BAUD2DIVISOR(baudrate)); in at91_usart_param()
216 WR4(bas, USART_RTOR, 20); in at91_usart_param()
218 WR4(bas, USART_RTOR, baudrate / 2000); in at91_usart_param()
219 WR4(bas, USART_CR, USART_CR_STTTO); in at91_usart_param()
290 WR4(bas, USART_CR, USART_CR_RSTSTA | USART_CR_RSTRX | USART_CR_RSTTX); in at91_usart_init()
291 WR4(bas, USART_CR, USART_CR_RXEN | USART_CR_TXEN); in at91_usart_init()
292 WR4(bas, USART_IDR, 0xffffffff); in at91_usart_init()
316 WR4(bas, USART_THR, c); in at91_usart_putc()
[all …]
HDat91_mci.c200 WR4(struct at91_mci_softc *sc, bus_size_t off, uint32_t val) in WR4() function
253 WR4(sc, PDC_PTCR, PDC_PTCR_TXTDIS | PDC_PTCR_RXTDIS); in at91_mci_pdc_disable()
254 WR4(sc, PDC_RPR, 0); in at91_mci_pdc_disable()
255 WR4(sc, PDC_RCR, 0); in at91_mci_pdc_disable()
256 WR4(sc, PDC_RNPR, 0); in at91_mci_pdc_disable()
257 WR4(sc, PDC_RNCR, 0); in at91_mci_pdc_disable()
258 WR4(sc, PDC_TPR, 0); in at91_mci_pdc_disable()
259 WR4(sc, PDC_TCR, 0); in at91_mci_pdc_disable()
260 WR4(sc, PDC_TNPR, 0); in at91_mci_pdc_disable()
261 WR4(sc, PDC_TNCR, 0); in at91_mci_pdc_disable()
[all …]
HDat91_aic.c70 WR4(struct aic_softc *sc, bus_size_t off, uint32_t val) in WR4() function
80 WR4(sc, IC_IDCR, 1 << nb); in arm_mask_irq()
92 WR4(sc, IC_EOICR, 1); in arm_get_next_irq()
102 WR4(sc, IC_IECR, 1 << nb); in arm_unmask_irq()
103 WR4(sc, IC_EOICR, 0); in arm_unmask_irq()
140 WR4(sc, IC_SVR + i * 4, i); in at91_aic_attach()
142 WR4(sc, IC_SMR + i * 4, soc_info.soc_data->soc_irq_prio[i]); in at91_aic_attach()
144 WR4(sc, IC_EOICR, 1); in at91_aic_attach()
147 WR4(sc, IC_SPU, 32); in at91_aic_attach()
149 WR4(sc, IC_DCR, 0); in at91_aic_attach()
[all …]
HDat91_pio.c84 WR4(struct at91_pio_softc *sc, bus_size_t off, uint32_t val) in WR4() function
185 WR4(sc, PIO_IDR, 0xffffffff); in at91_pio_attach()
368 WR4(sc, PIO_SODR, datapin); in at91_pio_bang32()
370 WR4(sc, PIO_CODR, datapin); in at91_pio_bang32()
372 WR4(sc, PIO_CODR, clockpin); in at91_pio_bang32()
373 WR4(sc, PIO_SODR, clockpin); in at91_pio_bang32()
385 WR4(sc, PIO_SODR, datapin); in at91_pio_bang()
387 WR4(sc, PIO_CODR, datapin); in at91_pio_bang()
389 WR4(sc, PIO_CODR, clockpin); in at91_pio_bang()
390 WR4(sc, PIO_SODR, clockpin); in at91_pio_bang()
[all …]
HDat91_twi.c83 WR4(struct at91_twi_softc *sc, bus_size_t off, uint32_t val) in WR4() function
158 WR4(sc, TWI_CR, TWI_CR_SWRST); in at91_twi_attach()
159 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); in at91_twi_attach()
160 WR4(sc, TWI_CWGR, sc->cwgr); in at91_twi_attach()
249 WR4(sc, TWI_IDR, status); in at91_twi_intr()
305 WR4(sc, TWI_CR, TWI_CR_SWRST); in at91_twi_rst_card()
306 WR4(sc, TWI_CR, TWI_CR_MSEN | TWI_CR_SVDIS); in at91_twi_rst_card()
307 WR4(sc, TWI_CWGR, sc->cwgr); in at91_twi_rst_card()
355 WR4(sc, TWI_MMR, TWI_MMR_DADR(msgs[i].slave) | rdwr); in at91_twi_transfer()
364 WR4(sc, TWI_CR, TWI_CR_START | TWI_CR_STOP); in at91_twi_transfer()
[all …]
HDat91_rtc.c87 WR4(struct at91_rtc_softc *sc, bus_size_t off, uint32_t val) in WR4() function
123 WR4(sc, RTC_SCCR, status); in at91_rtc_intr()
159 WR4(sc, RTC_IDR, 0xffffffff); in at91_rtc_attach()
160 WR4(sc, RTC_SCCR, 0x1f); in at91_rtc_attach()
161 WR4(sc, RTC_MR, 0); in at91_rtc_attach()
179 WR4(sc, RTC_CALR, 0); in at91_rtc_attach()
232 WR4(sc, RTC_IDR, 0xffffffff); in at91_rtc_deactivate()
318 WR4(sc, RTC_CR, RTC_CR_UPDCAL | RTC_CR_UPDTIM); in at91_rtc_settime()
321 WR4(sc, RTC_SCCR, RTC_SR_ACKUPD); in at91_rtc_settime()
327 WR4(sc, RTC_TIMR, RTC_TIMR_MK(ct.hour, ct.min, ct.sec)); in at91_rtc_settime()
[all …]
HDat91_st.c71 WR4(bus_size_t off, uint32_t val) in WR4() function
149 WR4(ST_WDMR, ST_WDMR_RSTEN | 2); in at91_st_cpu_reset()
150 WR4(ST_CR, ST_CR_WDRST); in at91_st_cpu_reset()
197 WR4(ST_IDR, 0xffffffff); in at91_st_activate()
282 WR4(ST_WDMR, wdog); in at91_st_watchdog()
283 WR4(ST_CR, ST_CR_WDRST); in at91_st_watchdog()
295 WR4(ST_RTMR, 1); in at91_st_initclocks()
297 WR4(ST_WDMR, 0); in at91_st_initclocks()
308 WR4(ST_PIMR, rel_value); in at91_st_initclocks()
311 WR4(ST_IER, ST_SR_PITS); in at91_st_initclocks()
HDif_ate.c174 WR4(struct ate_softc *sc, bus_size_t off, uint32_t val) in WR4() function
475 WR4(sc, ETH_HSL, 0xffffffff); in ate_setmcast()
476 WR4(sc, ETH_HSH, 0xffffffff); in ate_setmcast()
500 WR4(sc, ETH_HSL, mcaf[0]); in ate_setmcast()
501 WR4(sc, ETH_HSH, mcaf[1]); in ate_setmcast()
580 WR4(sc, ETH_RBQP, sc->rx_desc_phys); in ate_activate()
618 WR4(sc, ETHB_TBQP, sc->tx_desc_phys); in ate_activate()
621 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) | ETHB_UIO_CLKE); in ate_activate()
688 WR4(sc, ETHB_UIO, RD4(sc, ETHB_UIO) & ~ETHB_UIO_CLKE); in ate_deactivate()
739 WR4(sc, ETH_CFG, reg); in ate_stat_update()
[all …]
HDat91_pmc.c186 WR4(struct at91_pmc_softc *sc, bus_size_t off, uint32_t val) in WR4() function
245 WR4(sc, CKGR_PLLBR, value); in at91_pmc_set_pllb_mode()
263 WR4(sc, CKGR_UCKR, RD4(sc, CKGR_UCKR) | value); in at91_pmc_set_upll_mode()
267 WR4(sc, PMC_USB, PMC_USB_USBDIV(9) | PMC_USB_USBS); in at91_pmc_set_upll_mode()
268 WR4(sc, PMC_SCER, PMC_SCER_UHP_SAM9); in at91_pmc_set_upll_mode()
276 WR4(sc, on ? PMC_SCER : PMC_SCDR, clk->pmc_mask); in at91_pmc_set_sys_mode()
290 WR4(sc, on ? PMC_PCER : PMC_PCDR, clk->pmc_mask); in at91_pmc_set_periph_mode()
580 WR4(sc, PMC_SCDR, PMC_SCER_UHP | PMC_SCER_UDP); in at91_pmc_init_clock()
581 WR4(sc, PMC_SCER, PMC_SCER_MCKUDP); in at91_pmc_init_clock()
583 WR4(sc, PMC_SCDR, PMC_SCER_UHP_SAM9 | PMC_SCER_UDP_SAM9); in at91_pmc_init_clock()
[all …]
HDat91_ssc.c61 WR4(struct at91_ssc_softc *sc, bus_size_t off, uint32_t val) in WR4() function
142 WR4(sc, SSC_CR, SSC_CR_SWRST); in at91_ssc_attach()
143 WR4(sc, SSC_CMR, 0); // clock divider unused in at91_ssc_attach()
144 WR4(sc, SSC_RCMR, in at91_ssc_attach()
146 WR4(sc, SSC_RFMR, in at91_ssc_attach()
148 WR4(sc, SSC_TCMR, in at91_ssc_attach()
150 WR4(sc, SSC_TFMR, in at91_ssc_attach()
HDat91_rst.c75 WR4(struct at91_rst_softc *sc, bus_size_t off, uint32_t val) in WR4() function
91 WR4(at91_rst_sc, RST_MR, in at91_rst_cpu_reset()
94 WR4(at91_rst_sc, RST_CR, in at91_rst_cpu_reset()
154 WR4(at91_rst_sc, RST_MR, RST_MR_ERSTL(0xd) | RST_MR_URSIEN | RST_MR_KEY); in at91_rst_attach()
HDat91_wdt.c75 WR4(struct wdt_softc *sc, bus_size_t off, uint32_t val) in WR4() function
133 WR4(sc, WDT_CR, WDT_KEY|WDT_WDRSTT); in wdt_tick()
178 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)| in wdt_attach()
182 WR4(sc, WDT_MR, WDT_WDDBGHLT | WDT_WDD(0xC00)| in wdt_attach()
/trueos/sys/arm/freescale/imx/
HDimx6_ccm.c73 WR4(struct ccm_softc *sc, bus_size_t off, uint32_t val) in WR4() function
92 WR4(sc, CCM_CCGR0, 0x0000003f); /* ahpbdma, aipstz 1 & 2 busses */ in ccm_init_gates()
93 WR4(sc, CCM_CCGR1, 0x00300c00); /* gpt, enet */ in ccm_init_gates()
94 WR4(sc, CCM_CCGR2, 0x0fffffc0); /* ipmux & ipsync (bridges), iomux, i2c */ in ccm_init_gates()
95 WR4(sc, CCM_CCGR3, 0x3ff00000); /* DDR memory controller */ in ccm_init_gates()
96 WR4(sc, CCM_CCGR4, 0x0000f300); /* pl301 bus crossbar */ in ccm_init_gates()
97 WR4(sc, CCM_CCGR5, 0x0ffc00c0); /* uarts, ssi, sdma */ in ccm_init_gates()
98 WR4(sc, CCM_CCGR6, 0x000000ff); /* usdhc 1-4 */ in ccm_init_gates()
150 WR4(sc, CCM_CGPR, reg); in ccm_attach()
153 WR4(sc, CCM_CLPCR, reg); in ccm_attach()
[all …]
HDimx_sdhci.c170 WR4(struct imx_sdhci_softc *sc, bus_size_t off, uint32_t val) in WR4() function
385 WR4(sc, SDHC_PROT_CTRL, val32); in imx_sdhci_write_1()
398 WR4(sc, off & ~3, val32); in imx_sdhci_write_1()
414 WR4(sc, USDHC_MIX_CONTROL, val32); in imx_sdhci_write_2()
456 WR4(sc, SDHCI_INT_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in imx_sdhci_write_2()
457 WR4(sc, SDHCI_SIGNAL_ENABLE, slot->intmask | SDHCI_INT_RESPONSE); in imx_sdhci_write_2()
466 WR4(sc, off & ~3, val32); in imx_sdhci_write_2()
479 WR4(sc, off, val); in imx_sdhci_write_4()
513 WR4(sc, SDHC_VEND_SPEC, in imx_sdhc_set_clock()
515 WR4(sc, enable_reg, RD4(sc, enable_reg) & ~enable_bits); in imx_sdhc_set_clock()
[all …]
HDimx_iomux.c114 WR4(struct iomux_softc *sc, bus_size_t off, uint32_t val) in WR4() function
143 WR4(sc, reg, val); in iomux_configure_input()
165 WR4(sc, cfg->mux_reg, cfg->mux_val | sion); in iomux_configure_pins()
168 WR4(sc, cfg->padconf_reg, cfg->padconf_val); in iomux_configure_pins()
284 WR4(iomux_sc, regnum * 4, val); in imx_iomux_gpr_set()
300 WR4(iomux_sc, regnum * 4, val); in imx_iomux_gpr_set_masked()
/trueos/sys/arm/xilinx/
HDuart_dev_cdnc.c62 #define WR4(bas, reg, value) \ macro
215 WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv); in cdnc_uart_set_baud()
216 WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen); in cdnc_uart_set_baud()
263 WR4(bas, CDNC_UART_MODE_REG, mode_reg_value); in cdnc_uart_set_params()
276 WR4(bas, CDNC_UART_CTRL_REG, in cdnc_uart_hw_init()
280 WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL); in cdnc_uart_hw_init()
281 WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL); in cdnc_uart_hw_init()
284 WR4(bas, CDNC_UART_MODEM_STAT_REG, in cdnc_uart_hw_init()
289 WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2); in cdnc_uart_hw_init()
290 WR4(bas, CDNC_UART_RX_TIMEO_REG, 10); in cdnc_uart_hw_init()
[all …]
HDzy7_devcfg.c88 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
242 WR4(sc, ZY7_DEVCFG_CTRL, in zy7_devcfg_init_hw()
255 WR4(sc, ZY7_DEVCFG_MCTRL, RD4(sc, ZY7_DEVCFG_MCTRL) & in zy7_devcfg_init_hw()
271 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); in zy7_devcfg_reset_pl()
272 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); in zy7_devcfg_reset_pl()
276 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
285 WR4(sc, ZY7_DEVCFG_INT_MASK, ~0); in zy7_devcfg_reset_pl()
296 WR4(sc, ZY7_DEVCFG_CTRL, devcfg_ctl); in zy7_devcfg_reset_pl()
308 WR4(sc, ZY7_DEVCFG_INT_STATUS, ZY7_DEVCFG_INT_ALL); in zy7_devcfg_reset_pl()
309 WR4(sc, ZY7_DEVCFG_INT_MASK, ~ZY7_DEVCFG_INT_PCFG_INIT_PE); in zy7_devcfg_reset_pl()
[all …]
HDzy7_gpio.c95 #define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val)) macro
196 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), in zy7_gpio_pin_setflags()
200 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
204 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
209 WR4(sc, ZY7_GPIO_DIRM(pin >> 5), in zy7_gpio_pin_setflags()
211 WR4(sc, ZY7_GPIO_OEN(pin >> 5), in zy7_gpio_pin_setflags()
231 WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5), in zy7_gpio_pin_set()
235 WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5), in zy7_gpio_pin_set()
267 WR4(sc, ZY7_GPIO_DATA(pin >> 5), in zy7_gpio_pin_toggle()
295 WR4(sc, ZY7_GPIO_DATA(i), 0); in zy7_gpio_hw_reset()
[all …]
HDzy7_slcr.c78 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
118 WR4(sc, ZY7_SLCR_UNLOCK, ZY7_SLCR_UNLOCK_MAGIC); in zy7_slcr_unlock()
126 WR4(sc, ZY7_SLCR_LOCK, ZY7_SLCR_LOCK_MAGIC); in zy7_slcr_lock()
141 WR4(sc, ZY7_SLCR_REBOOT_STAT, in zy7_slcr_cpu_reset()
145 WR4(sc, ZY7_SLCR_PSS_RST_CTRL, ZY7_SLCR_PSS_RST_CTRL_SOFT_RESET); in zy7_slcr_cpu_reset()
168 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, ZY7_SLCR_FPGA_RST_CTRL_RST_ALL); in zy7_slcr_preload_pl()
171 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, 0); in zy7_slcr_preload_pl()
199 WR4(sc, ZY7_SLCR_LVL_SHFTR_EN, ZY7_SLCR_LVL_SHFTR_EN_ALL); in zy7_slcr_postload_pl()
202 WR4(sc, ZY7_SLCR_FPGA_RST_CTRL, 0); in zy7_slcr_postload_pl()
244 WR4(sc, unit ? ZY7_SLCR_GEM1_CLK_CTRL : ZY7_SLCR_GEM0_CLK_CTRL, in cgem_set_ref_clk()
/trueos/sys/dev/ffec/
HDif_ffec.c216 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val) in WR4() function
309 WR4(sc, FEC_IER_REG, FEC_IER_MII); in ffec_miibus_readreg()
311 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ | in ffec_miibus_readreg()
333 WR4(sc, FEC_IER_REG, FEC_IER_MII); in ffec_miibus_writereg()
335 WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE | in ffec_miibus_writereg()
418 WR4(sc, FEC_RCR_REG, rcr); in ffec_miibus_statchg()
419 WR4(sc, FEC_TCR_REG, tcr); in ffec_miibus_statchg()
420 WR4(sc, FEC_ECR_REG, ecr); in ffec_miibus_statchg()
463 WR4(sc, FEC_RMON_R_PACKETS, 0); in ffec_clear_stats()
464 WR4(sc, FEC_RMON_R_MC_PKT, 0); in ffec_clear_stats()
[all …]
/trueos/sys/arm/xscale/ixp425/
HDixp425_wdog.c60 WR4(struct ixpwdog_softc *sc, bus_size_t off, uint32_t val) in WR4() function
71 WR4(sc, IXP425_OST_WDOG_KEY, OST_WDOG_KEY_MAJICK); in ixp425_watchdog()
73 WR4(sc, IXP425_OST_WDOG_ENAB, 0); in ixp425_watchdog()
75 WR4(sc, IXP425_OST_WDOG, 2<<(u - 4)); in ixp425_watchdog()
77 WR4(sc, IXP425_OST_WDOG_ENAB, in ixp425_watchdog()
82 WR4(sc, IXP425_OST_WDOG_ENAB, 0); in ixp425_watchdog()
84 WR4(sc, IXP425_OST_WDOG_KEY, 0); in ixp425_watchdog()
HDif_npe.c206 WR4(struct npe_softc *sc, bus_size_t off, uint32_t val) in WR4() function
461 WR4(sc, NPE_MAC_ADDR_MASK(i), mask[i]); in npe_setmcast()
462 WR4(sc, NPE_MAC_ADDR(i), addr[i]); in npe_setmcast()
661 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_RESET); in npe_mac_reset()
664 WR4(sc, NPE_MAC_CORE_CNTRL, NPE_CORE_MDC_EN); in npe_mac_reset()
966 WR4(sc, NPE_MAC_UNI_ADDR_1, eaddr[0]); in npe_setmac()
967 WR4(sc, NPE_MAC_UNI_ADDR_2, eaddr[1]); in npe_setmac()
968 WR4(sc, NPE_MAC_UNI_ADDR_3, eaddr[2]); in npe_setmac()
969 WR4(sc, NPE_MAC_UNI_ADDR_4, eaddr[3]); in npe_setmac()
970 WR4(sc, NPE_MAC_UNI_ADDR_5, eaddr[4]); in npe_setmac()
[all …]
/trueos/sys/dev/cadence/
HDif_cgem.c195 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) macro
259 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | in cgem_get_mac()
261 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); in cgem_get_mac()
264 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); in cgem_get_mac()
265 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); in cgem_get_mac()
343 WR4(sc, CGEM_HASH_TOP, hash_hi); in cgem_rx_filter()
344 WR4(sc, CGEM_HASH_BOT, hash_lo); in cgem_rx_filter()
345 WR4(sc, CGEM_NET_CFG, net_cfg); in cgem_rx_filter()
781 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | in cgem_start_locked()
888 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow & in cgem_tick()
[all …]
/trueos/sys/dev/sdhci/
HDsdhci.c69 #define WR4(slot, off, val) SDHCI_WRITE_4((slot)->bus, (slot), (off), (val)) macro
225 WR4(slot, SDHCI_INT_ENABLE, slot->intmask); in sdhci_init()
226 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask); in sdhci_init()
408 WR4(slot, SDHCI_BUFFER, data); in sdhci_write_block_pio()
422 WR4(slot, SDHCI_BUFFER, data); in sdhci_write_block_pio()
694 WR4(slot, SDHCI_SIGNAL_ENABLE, 0); in sdhci_generic_update_ios()
866 WR4(slot, SDHCI_SIGNAL_ENABLE, in sdhci_start_command()
870 WR4(slot, SDHCI_ARGUMENT, cmd->arg); in sdhci_start_command()
888 WR4(slot, SDHCI_SIGNAL_ENABLE, slot->intmask |= SDHCI_INT_RESPONSE); in sdhci_finish_command()
978 WR4(slot, SDHCI_DMA_ADDRESS, slot->paddr); in sdhci_start_data()
[all …]

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