216 WR4(struct ffec_softc *sc, bus_size_t off, uint32_t val)  in WR4()  function
309 	WR4(sc, FEC_IER_REG, FEC_IER_MII);  in ffec_miibus_readreg()
311 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_READ |  in ffec_miibus_readreg()
333 	WR4(sc, FEC_IER_REG, FEC_IER_MII);  in ffec_miibus_writereg()
335 	WR4(sc, FEC_MMFR_REG, FEC_MMFR_OP_WRITE |  in ffec_miibus_writereg()
418 	WR4(sc, FEC_RCR_REG, rcr);  in ffec_miibus_statchg()
419 	WR4(sc, FEC_TCR_REG, tcr);  in ffec_miibus_statchg()
420 	WR4(sc, FEC_ECR_REG, ecr);  in ffec_miibus_statchg()
463 	WR4(sc, FEC_RMON_R_PACKETS, 0);  in ffec_clear_stats()
464 	WR4(sc, FEC_RMON_R_MC_PKT, 0);  in ffec_clear_stats()
465 	WR4(sc, FEC_RMON_R_CRC_ALIGN, 0);  in ffec_clear_stats()
466 	WR4(sc, FEC_RMON_R_UNDERSIZE, 0);  in ffec_clear_stats()
467 	WR4(sc, FEC_RMON_R_OVERSIZE, 0);  in ffec_clear_stats()
468 	WR4(sc, FEC_RMON_R_FRAG, 0);  in ffec_clear_stats()
469 	WR4(sc, FEC_RMON_R_JAB, 0);  in ffec_clear_stats()
470 	WR4(sc, FEC_RMON_T_PACKETS, 0);  in ffec_clear_stats()
471 	WR4(sc, FEC_RMON_T_MC_PKT, 0);  in ffec_clear_stats()
472 	WR4(sc, FEC_RMON_T_CRC_ALIGN, 0);  in ffec_clear_stats()
473 	WR4(sc, FEC_RMON_T_UNDERSIZE, 0);  in ffec_clear_stats()
474 	WR4(sc, FEC_RMON_T_OVERSIZE , 0);  in ffec_clear_stats()
475 	WR4(sc, FEC_RMON_T_FRAG, 0);  in ffec_clear_stats()
476 	WR4(sc, FEC_RMON_T_JAB, 0);  in ffec_clear_stats()
477 	WR4(sc, FEC_RMON_T_COL, 0);  in ffec_clear_stats()
657 		WR4(sc, FEC_TDAR_REG, FEC_TDAR_TDAR);  in ffec_txstart_locked()
901 		WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);  in ffec_rxfinish_locked()
978 	WR4(sc, FEC_GAUR_REG, (uint32_t)(ghash >> 32));  in ffec_setup_rxfilter()
979 	WR4(sc, FEC_GALR_REG, (uint32_t)ghash);  in ffec_setup_rxfilter()
993 	WR4(sc, FEC_IAUR_REG, (uint32_t)(ihash >> 32));  in ffec_setup_rxfilter()
994 	WR4(sc, FEC_IALR_REG, (uint32_t)ihash);  in ffec_setup_rxfilter()
1000 	WR4(sc, FEC_PALR_REG, (eaddr[0] << 24) | (eaddr[1] << 16) |  in ffec_setup_rxfilter()
1002 	WR4(sc, FEC_PAUR_REG, (eaddr[4] << 24) | (eaddr[5] << 16));  in ffec_setup_rxfilter()
1024 	WR4(sc, FEC_ECR_REG, RD4(sc, FEC_ECR_REG) & ~FEC_ECR_ETHEREN);  in ffec_stop_locked()
1025 	WR4(sc, FEC_IEM_REG, 0x00000000);  in ffec_stop_locked()
1026 	WR4(sc, FEC_IER_REG, 0xffffffff);  in ffec_stop_locked()
1101 	WR4(sc, FEC_IEM_REG, 0x00000000);  in ffec_init_locked()
1102 	WR4(sc, FEC_IER_REG, 0xffffffff);  in ffec_init_locked()
1119 	WR4(sc, FEC_TFWR_REG, FEC_TFWR_STRFWD | FEC_TFWR_TWFR_128BYTE);  in ffec_init_locked()
1125 	WR4(sc, FEC_RCR_REG, (maxfl << FEC_RCR_MAX_FL_SHIFT));  in ffec_init_locked()
1133 	WR4(sc, FEC_TCR_REG, 0);  in ffec_init_locked()
1140 	WR4(sc, FEC_OPD_REG, 0x00010020);  in ffec_init_locked()
1164 	WR4(sc, FEC_MRBR_REG, maxfl << FEC_MRBR_R_BUF_SIZE_SHIFT);  in ffec_init_locked()
1171 	WR4(sc, FEC_FTRL_REG, maxfl);  in ffec_init_locked()
1183 	WR4(sc, FEC_RDSR_REG, sc->rxdesc_ring_paddr);  in ffec_init_locked()
1184 	WR4(sc, FEC_TDSR_REG, sc->txdesc_ring_paddr);  in ffec_init_locked()
1193 	WR4(sc, FEC_IEM_REG, FEC_IER_TXF | FEC_IER_RXF | FEC_IER_EBERR);  in ffec_init_locked()
1199 	WR4(sc, FEC_MIBC_REG, regval | FEC_MIBC_DIS);  in ffec_init_locked()
1201 	WR4(sc, FEC_MIBC_REG, regval & ~FEC_MIBC_DIS);  in ffec_init_locked()
1217 	WR4(sc, FEC_ECR_REG, regval);  in ffec_init_locked()
1232 	WR4(sc, FEC_RDAR_REG, FEC_RDAR_RDAR);  in ffec_init_locked()
1258 		WR4(sc, FEC_IER_REG, FEC_IER_TXF);  in ffec_intr()
1263 		WR4(sc, FEC_IER_REG, FEC_IER_RXF);  in ffec_intr()
1276 		WR4(sc, FEC_IER_REG, FEC_IER_EBERR);  in ffec_intr()
1631 	WR4(sc, FEC_ECR_REG, FEC_ECR_RESET);  in ffec_attach()
1672 	WR4(sc, FEC_MSCR_REG, mscr);  in ffec_attach()