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Searched refs:TRI (Results 1 – 25 of 194) sorted by relevance

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/trueos/contrib/llvm/lib/Target/R600/
HDSIFixSGPRCopies.cpp86 const TargetRegisterClass *inferRegClassFromUses(const SIRegisterInfo *TRI,
90 const TargetRegisterClass *inferRegClassFromDef(const SIRegisterInfo *TRI,
94 bool isVGPRToSGPRCopy(const MachineInstr &Copy, const SIRegisterInfo *TRI,
116 static bool hasVGPROperands(const MachineInstr &MI, const SIRegisterInfo *TRI) { in hasVGPROperands() argument
123 if (TRI->hasVGPRs(MRI.getRegClass(MI.getOperand(i).getReg()))) in hasVGPROperands()
133 const SIRegisterInfo *TRI, in inferRegClassFromUses() argument
143 RC = TRI->getSubRegClass(RC, SubReg); in inferRegClassFromUses()
148 RC = TRI->getCommonSubClass(RC, inferRegClassFromUses(TRI, MRI, in inferRegClassFromUses()
159 const SIRegisterInfo *TRI, in inferRegClassFromDef() argument
164 const TargetRegisterClass *RC = TRI->getPhysRegClass(Reg); in inferRegClassFromDef()
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HDR600ExpandSpecialInstrs.cpp61 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
169 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
177 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
190 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() local
193 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
196 bool Mask = (Chan != TRI.getHWRegChan(DstReg)); in runOnMachineFunction()
220 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
221 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
222 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
276 unsigned SubRegIndex = TRI.getSubRegFromChannel(Chan); in runOnMachineFunction()
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/trueos/contrib/llvm/lib/CodeGen/
HDRegisterClassInfo.cpp32 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) in RegisterClassInfo()
40 if (MF->getTarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
41 TRI = MF->getTarget().getRegisterInfo(); in runOnMachineFunction()
42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
43 unsigned NumPSets = TRI->getNumRegPressureSets(); in runOnMachineFunction()
50 const MCPhysReg *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
55 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
57 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in runOnMachineFunction()
101 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
120 unsigned Cost = TRI->getCostPerUse(PhysReg); in compute()
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HDLiveRegMatrix.cpp50 TRI = MF.getTarget().getRegisterInfo(); in runOnMachineFunction()
55 unsigned NumRegUnits = TRI->getNumRegUnits(); in runOnMachineFunction()
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
74 << " to " << PrintReg(PhysReg, TRI) << ':'); in assign()
78 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in assign()
79 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); in assign()
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
89 << " from " << PrintReg(PhysReg, TRI) << ':'); in unassign()
91 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in unassign()
92 DEBUG(dbgs() << ' ' << PrintRegUnit(*Units, TRI)); in unassign()
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HDAggressiveAntiDepBreaker.cpp122 TRI(MF.getTarget().getRegisterInfo()), in AggressiveAntiDepBreaker()
128 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
138 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
148 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
159 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
172 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
175 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in StartBlock()
203 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
212 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs()
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HDRegisterScavenging.cpp34 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in setUsed()
40 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) in isAliasUsed()
74 TRI = TM.getRegisterInfo(); in enterBasicBlock()
77 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && in enterBasicBlock()
87 NumPhysRegs = TRI->getNumRegs(); in enterBasicBlock()
94 const uint16_t *CSRegs = TRI->getCalleeSavedRegs(&MF); in enterBasicBlock()
107 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addRegWithSubRegs()
220 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in forward()
237 isLiveInButUnusedBefore(Reg, MI, MBB, TRI, MRI)) && in forward()
262 DEBUG(dbgs() << "Scavenger found unused reg: " << TRI->getName(*I) << in FindUnusedReg()
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HDTargetRegisterInfo.cpp43 else if (TRI && Reg < TRI->getNumRegs()) in print()
44 OS << '%' << TRI->getName(Reg); in print()
48 if (TRI) in print()
49 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
57 if (!TRI) { in print()
63 if (Unit >= TRI->getNumRegUnits()) { in print()
69 MCRegUnitRootIterator Roots(Unit, TRI); in print()
71 OS << TRI->getName(*Roots); in print()
73 OS << '~' << TRI->getName(*Roots); in print()
77 if (TRI && TRI->isVirtualRegister(Unit)) { in print()
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HDCriticalAntiDepBreaker.cpp34 TRI(MF.getTarget().getRegisterInfo()), in CriticalAntiDepBreaker()
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), in CriticalAntiDepBreaker()
37 KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
38 DefIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
39 KeepRegs(TRI->getNumRegs(), false) {} in CriticalAntiDepBreaker()
46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
65 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
78 for (const uint16_t *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) { in StartBlock()
80 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) { in StartBlock()
100 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
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HDMachineCopyPropagation.cpp35 const TargetRegisterInfo *TRI; member in __anona31b49610111::MachineCopyPropagation
68 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) { in SourceNoLongerAvailable()
77 for (MCSubRegIterator SR(MappedDef, TRI); SR.isValid(); ++SR) in SourceNoLongerAvailable()
114 const TargetRegisterInfo *TRI) { in isNopCopy() argument
118 if (TRI->isSubRegister(SrcSrc, Def)) { in isNopCopy()
120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy()
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
164 isNopCopy(CopyMI, Def, Src, TRI)) { in CopyPropagateBlock()
182 I->clearRegisterKills(Def, TRI); in CopyPropagateBlock()
192 for (MCRegAliasIterator AI(Src, TRI, true); AI.isValid(); ++AI) { in CopyPropagateBlock()
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HDLiveVariables.cpp197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef()
219 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true); in FindLastPartialDef()
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
274 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in HandlePhysRegUse()
290 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastRefOrPartRef()
339 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill()
353 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid(); in HandlePhysRegKill()
369 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
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HDRegAllocFast.cpp58 const TargetRegisterInfo *TRI; member in __anon61ebfa040111::RAFast
125 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in markRegUsedInInstr()
131 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) in isRegUsedInInstr()
240 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
285 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->VirtReg, TRI) in spillVirtReg()
286 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); in spillVirtReg()
365 for (MCRegAliasIterator AI(PhysReg, TRI, false); AI.isValid(); ++AI) { in usePhysReg()
371 assert(TRI->isSuperRegister(PhysReg, Alias) && in usePhysReg()
375 MO.getParent()->addRegisterKilled(Alias, TRI, true); in usePhysReg()
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HDLocalStackSlotAllocation.cpp89 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); in runOnMachineFunction() local
94 if (!TRI->requiresVirtualBaseRegisters(MF) || LocalObjectCount == 0) in runOnMachineFunction()
204 const TargetRegisterInfo *TRI) { in lookupCandidateBaseReg() argument
208 return TRI->isFrameOffsetLegal(MI, Offset); in lookupCandidateBaseReg()
221 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); in insertFrameReferenceRegisters() local
256 if (!TRI->needsFrameBaseReg(MI, LocalOffset)) in insertFrameReferenceRegisters()
308 LocalOffset, MI, TRI)) { in insertFrameReferenceRegisters()
315 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx); in insertFrameReferenceRegisters()
332 FRN.getLocalOffset(), MIN, TRI); in insertFrameReferenceRegisters()
342 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF); in insertFrameReferenceRegisters()
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HDInterferenceCache.cpp32 TRI = tri; in init()
33 PhysRegEntries.assign(TRI->getNumRegs(), 0); in init()
41 if (!Entries[E].valid(LIUArray, TRI)) in get()
42 Entries[E].revalidate(LIUArray, TRI); in get()
56 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
65 const TargetRegisterInfo *TRI) { in revalidate() argument
71 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) in revalidate()
77 const TargetRegisterInfo *TRI, in reset() argument
88 for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) { in reset()
95 const TargetRegisterInfo *TRI) { in valid() argument
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HDVirtRegMap.cpp56 TRI = mf.getTarget().getRegisterInfo(); in runOnMachineFunction()
122 OS << '[' << PrintReg(Reg, TRI) << " -> " in print()
123 << PrintReg(Virt2PhysMap[Reg], TRI) << "] " in print()
131 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] in print()
157 const TargetRegisterInfo *TRI; member in __anon6933ec6e0111::VirtRegRewriter
205 TRI = TM->getRegisterInfo(); in runOnMachineFunction()
337 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); in rewrite()
349 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true); in rewrite()
352 MI->addRegisterDead(SuperDeads.pop_back_val(), TRI, true); in rewrite()
355 MI->addRegisterDefined(SuperDefs.pop_back_val(), TRI); in rewrite()
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HDRegisterCoalescer.cpp82 const TargetRegisterInfo* TRI; member in __anon3fd7f4430111::RegisterCoalescer
259 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) in setRegisters()
277 Dst = TRI.getSubReg(Dst, DstSub); in setRegisters()
284 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src)); in setRegisters()
301 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
308 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
312 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
315 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
354 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub)) in isCoalescable()
372 Dst = TRI.getSubReg(Dst, DstSub); in isCoalescable()
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HDRegisterPressure.cpp46 const TargetRegisterInfo *TRI) { in dumpRegSetPressure() argument
50 dbgs() << TRI->getRegPressureSetName(i) << "=" << SetPressure[i] << '\n'; in dumpRegSetPressure()
58 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const { in dump()
60 dumpRegSetPressure(MaxSetPressure, TRI); in dump()
63 dbgs() << PrintReg(LiveInRegs[i], TRI) << " "; in dump()
67 dbgs() << PrintReg(LiveOutRegs[i], TRI) << " "; in dump()
74 dumpRegSetPressure(CurrSetPressure, TRI); in dump()
76 P.dump(TRI); in dump()
187 TRI = MF->getTarget().getRegisterInfo(); in init()
199 CurrSetPressure.assign(TRI->getNumRegPressureSets(), 0); in init()
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HDInterferenceCache.h25 const TargetRegisterInfo *TRI; variable
112 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
115 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 const TargetRegisterInfo *TRI,
150 InterferenceCache() : TRI(0), LIUArray(0), MF(0), RoundRobin(0) {} in InterferenceCache()
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonFrameLowering.cpp212 unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) { in uniqueSuperReg() argument
213 MCSuperRegIterator SRI(Reg, TRI); in uniqueSuperReg()
226 const TargetRegisterInfo *TRI) const { in spillCalleeSavedRegisters()
247 unsigned SuperReg = uniqueSuperReg(Reg, TRI); in spillCalleeSavedRegisters()
252 unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI); in spillCalleeSavedRegisters()
253 SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg); in spillCalleeSavedRegisters()
260 CSI[i+1].getFrameIdx(), SuperRegClass, TRI); in spillCalleeSavedRegisters()
266 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters()
268 TRI); in spillCalleeSavedRegisters()
280 const TargetRegisterInfo *TRI) const { in restoreCalleeSavedRegisters()
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HDHexagonCopyToCombine.cpp61 const TargetRegisterInfo *TRI; member in __anon8eca2b7d0111::HexagonCopyToCombine
172 static bool areCombinableOperations(const TargetRegisterInfo *TRI, in areCombinableOperations() argument
184 static_cast<const HexagonRegisterInfo *>(TRI); in areCombinableOperations()
224 const TargetRegisterInfo *TRI) { in isUnsafeToMoveAcross() argument
225 return (UseReg && (I->modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
226 I->modifiesRegister(DestReg, TRI) || in isUnsafeToMoveAcross()
227 I->readsRegister(DestReg, TRI) || in isUnsafeToMoveAcross()
245 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI)) in isSafeToMoveTogether()
275 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) { in isSafeToMoveTogether()
282 I->readsRegister(KilledOperand, TRI)) in isSafeToMoveTogether()
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/trueos/contrib/llvm/lib/Target/AArch64/
HDAArch64AsmPrinter.cpp34 const TargetRegisterInfo *TRI, in printModifiedFPRAsmOperand() argument
39 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { in printModifiedFPRAsmOperand()
41 O << RegType << TRI->getEncodingValue(MO.getReg()); in printModifiedFPRAsmOperand()
53 const TargetRegisterInfo *TRI, in printModifiedGPRAsmOperand() argument
67 for (MCRegAliasIterator AR(MO.getReg(), TRI, true); AR.isValid(); ++AR) { in printModifiedGPRAsmOperand()
148 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); in PrintAsmOperand() local
161 if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
168 if (!printModifiedGPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
191 if (!printModifiedFPRAsmOperand(MI->getOperand(OpNum), TRI, in PrintAsmOperand()
228 if (printModifiedFPRAsmOperand(MO, TRI, 'v', O)) in PrintAsmOperand()
/trueos/contrib/llvm/include/llvm/CodeGen/
HDMachineInstr.h724 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
725 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
745 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
746 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
753 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
754 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
760 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
761 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
768 const TargetRegisterInfo *TRI = NULL) const {
769 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
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/trueos/contrib/llvm/lib/Target/Mips/
HDMipsInstrInfo.h90 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot() argument
91 storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0); in storeRegToStackSlot()
98 const TargetRegisterInfo *TRI) const { in loadRegFromStackSlot() argument
99 loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0); in loadRegFromStackSlot()
106 const TargetRegisterInfo *TRI,
113 const TargetRegisterInfo *TRI,
/trueos/contrib/llvm/lib/Target/ARM/
HDARMBaseInstrInfo.cpp737 const TargetRegisterInfo *TRI = &getRegisterInfo(); in copyPhysReg() local
741 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) { in copyPhysReg()
749 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing); in copyPhysReg()
750 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing); in copyPhysReg()
766 Mov->addRegisterDefined(DestReg, TRI); in copyPhysReg()
768 Mov->addRegisterKilled(SrcReg, TRI); in copyPhysReg()
774 const TargetRegisterInfo *TRI) const { in AddDReg()
779 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State); in AddDReg()
787 const TargetRegisterInfo *TRI) const { in storeRegToStackSlot()
821 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
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HDThumb2ITBlockPass.cpp33 const TargetRegisterInfo *TRI; member in __anon8832d5bf0111::Thumb2ITBlockPass
58 const TargetRegisterInfo *TRI) { in TrackDefUses() argument
77 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses()
84 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true); in TrackDefUses()
179 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
229 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
258 TRI = TM.getRegisterInfo(); in runOnMachineFunction()
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZElimCompare.cpp67 : MachineFunctionPass(ID), TII(0), TRI(0) {} in SystemZElimCompare()
89 const TargetRegisterInfo *TRI; member in __anon0dc59e9a0111::SystemZElimCompare
146 if (MOReg == Reg || TRI->regsOverlap(MOReg, Reg)) { in getRegReferences()
291 int CCDef = MI->findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI); in adjustCCMasksForInstr()
298 MBBI->clearRegisterKills(SystemZ::CC, TRI); in adjustCCMasksForInstr()
387 if (MBBI->modifiesRegister(SrcReg, TRI) || in fuseCompareAndBranch()
388 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI))) in fuseCompareAndBranch()
398 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI); in fuseCompareAndBranch()
417 MBBI->clearRegisterKills(SrcReg, TRI); in fuseCompareAndBranch()
419 MBBI->clearRegisterKills(SrcReg2, TRI); in fuseCompareAndBranch()
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