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Searched refs:RS (Results 1 – 25 of 195) sorted by relevance

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/trueos/contrib/binutils/opcodes/
HDppc-opc.c393 #define RS RBS + 1 macro
394 #define RT RS
400 #define RSQ RS + 1
1806 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } },
1807 { "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } },
1808 { "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } },
1809 { "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } },
1810 { "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } },
1811 { "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } },
1812 { "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } },
[all …]
/trueos/contrib/llvm/lib/Target/PowerPC/
HDPPCJITInfo.cpp27 #define BUILD_ADDIS(RD,RS,IMM16) \ argument
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
29 #define BUILD_ORI(RD,RS,UIMM16) \ argument
30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_ORIS(RD,RS,UIMM16) \ argument
32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
33 #define BUILD_RLDICR(RD,RS,SH,ME) \ argument
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
36 #define BUILD_MTSPR(RS,SPR) \ argument
37 ((31 << 26) | ((RS) << 21) | ((SPR) << 16) | (467 << 1))
[all …]
HDPPCFrameLowering.h49 RegScavenger *RS = NULL) const;
51 RegScavenger *RS = NULL) const;
52 void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
/trueos/contrib/llvm/lib/CodeGen/
HDPrologEpilogInserter.cpp108 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; in runOnMachineFunction()
118 TFI->processFunctionBeforeCalleeSavedScan(Fn, RS); in runOnMachineFunction()
134 TFI->processFunctionBeforeFrameFinalized(Fn, RS); in runOnMachineFunction()
168 delete RS; in runOnMachineFunction()
490 if (RS && EarlyScavengingSlots) { in calculateFrameObjectOffsets()
492 RS->getScavengingFrameIndices(SFIs); in calculateFrameObjectOffsets()
538 if (RS && RS->isScavengingFrameIndex((int)i)) in calculateFrameObjectOffsets()
560 if (RS && RS->isScavengingFrameIndex((int)i)) in calculateFrameObjectOffsets()
574 if (RS && !EarlyScavengingSlots) { in calculateFrameObjectOffsets()
576 RS->getScavengingFrameIndices(SFIs); in calculateFrameObjectOffsets()
[all …]
HDTailDuplication.cpp66 OwningPtr<RegScavenger> RS; member in __anon898cb4d30111::TailDuplicatePass
136 RS.reset(); in runOnMachineFunction()
138 RS.reset(new RegScavenger()); in runOnMachineFunction()
785 if (RS && !TailBB->livein_empty()) { in TailDuplicate()
787 RS->enterBasicBlock(PredBB); in TailDuplicate()
789 RS->forward(prior(PredBB->end())); in TailDuplicate()
791 RS->getRegsUsed(RegsLiveAtExit, false); in TailDuplicate()
/trueos/contrib/llvm/lib/Target/Hexagon/
HDHexagonFixupHwLoops.cpp65 RegScavenger &RS);
119 RegScavenger RS; in fixupLoopInstrs() local
125 RS.enterBasicBlock(MBB); in fixupLoopInstrs()
132 RS.forward(MII); in fixupLoopInstrs()
139 convertLoopInstr(MF, MII, RS); in fixupLoopInstrs()
160 RegScavenger &RS) { in convertLoopInstr() argument
164 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0); in convertLoopInstr()
/trueos/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
HDMallocChecker.cpp92 static RefState getEscaped(const RefState *RS) { in getEscaped() argument
93 return RefState(Escaped, RS->getStmt(), RS->getAllocationFamily()); in getEscaped()
315 const Expr *DeallocExpr, const RefState *RS,
1120 const RefState *RS = C.getState()->get<RegionState>(Sym); in isTrackedByCurrentChecker() local
1121 assert(RS); in isTrackedByCurrentChecker()
1122 return isTrackedByCurrentChecker(RS->getAllocationFamily()); in isTrackedByCurrentChecker()
1262 const RefState *RS, in ReportMismatchedDealloc() argument
1277 const Expr *AllocExpr = cast<Expr>(RS->getStmt()); in ReportMismatchedDealloc()
1299 printExpectedDeallocName(os, RS->getAllocationFamily()); in ReportMismatchedDealloc()
1583 const RefState *RS = C.getState()->get<RegionState>(Sym); in reportLeak() local
[all …]
HDReturnPointerRangeChecker.cpp30 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
34 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
38 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
HDReturnUndefChecker.cpp35 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
39 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
41 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
HDStackAddrEscapeChecker.cpp35 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const;
119 void StackAddrEscapeChecker::checkPreStmt(const ReturnStmt *RS, in checkPreStmt() argument
122 const Expr *RetE = RS->getRetValue(); in checkPreStmt()
/trueos/contrib/llvm/lib/Analysis/
HDCostModel.cpp168 ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(R); in matchPairwiseReductionAtLevel() local
169 if (!RS && Level) in matchPairwiseReductionAtLevel()
173 if (!Level && !RS && !LS) in matchPairwiseReductionAtLevel()
178 Value *NextLevelOpR = RS ? RS->getOperand(0) : 0; in matchPairwiseReductionAtLevel()
214 if (!matchPairwiseShuffleMask(RS, false, Level)) in matchPairwiseReductionAtLevel()
216 } else if (matchPairwiseShuffleMask(RS, true, Level)) { in matchPairwiseReductionAtLevel()
/trueos/contrib/llvm/lib/DebugInfo/
HDDWARFCompileUnit.h20 StringRef RS, StringRef SS, StringRef SOS, StringRef AOS, in DWARFCompileUnit() argument
22 : DWARFUnit(DA, IS, AS, RS, SS, SOS, AOS, M, LE) {} in DWARFCompileUnit()
HDDWARFTypeUnit.h23 StringRef RS, StringRef SS, StringRef SOS, StringRef AOS, in DWARFTypeUnit() argument
25 : DWARFUnit(DA, IS, AS, RS, SS, SOS, AOS, M, LE) {} in DWARFTypeUnit()
HDDWARFUnit.h68 StringRef RS, StringRef SS, StringRef SOS, StringRef AOS,
79 void setRangesSection(StringRef RS, uint32_t Base) { in setRangesSection() argument
80 RangeSection = RS; in setRangesSection()
/trueos/sys/boot/amd64/efi/
HDmain.c143 RS->ResetSystem(EfiResetCold, EFI_SUCCESS, 23, in command_reboot()
344 status = RS->GetNextVariableName(&varsz, NULL, NULL); in command_nvram()
347 status = RS->GetNextVariableName(&varsz, var, in command_nvram()
355 status = RS->GetVariable(var, &varguid, NULL, &datasz, in command_nvram()
359 status = RS->GetVariable(var, &varguid, NULL, &datasz, in command_nvram()
/trueos/contrib/llvm/lib/Target/Sparc/
HDSparcRegisterInfo.h46 RegScavenger *RS = NULL) const;
49 RegScavenger *RS = NULL) const;
/trueos/contrib/llvm/lib/Target/Mips/
HDMipsRegisterInfo.h63 RegScavenger *RS = NULL) const;
66 RegScavenger *RS = NULL) const;
/trueos/contrib/llvm/lib/Target/SystemZ/
HDSystemZFrameLowering.h38 RegScavenger *RS) const LLVM_OVERRIDE;
52 RegScavenger *RS) const;
/trueos/contrib/llvm/include/llvm/Target/
HDTargetFrameLowering.h193 RegScavenger *RS = NULL) const {
203 RegScavenger *RS = NULL) const {
/trueos/sys/mips/conf/
HDROUTERSTATION.hints11 # Uncomment this hint for RS (not PRO)
16 # should be 100 for RS
/trueos/contrib/llvm/lib/Target/XCore/
HDXCoreRegisterInfo.cpp107 RegScavenger *RS) const { in eliminateFrameIndex()
164 if (!RS) in eliminateFrameIndex()
167 unsigned ScratchReg = RS->scavengeRegister(&XCore::GRRegsRegClass, II, in eliminateFrameIndex()
/trueos/sys/boot/efi/libefi/
HDlibefi.c38 EFI_RUNTIME_SERVICES *RS; variable
97 RS = ST->RuntimeServices; in efi_main()
/trueos/contrib/llvm/lib/Target/NVPTX/
HDNVPTXRegisterInfo.td36 def RS#i : NVPTXReg<"%rs"#i>; // 16-bit
53 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
/trueos/contrib/gcc/config/rs6000/
HDrs6000-modes.def1 /* Definitions of target machine for GNU compiler, for IBM RS/6000.
33 For the RS/6000, we need separate modes when unsigned (logical) comparisons
/trueos/gnu/usr.bin/rcs/doc/
HDrcs_func.ms11 .RS
26 .RS
65 .RS

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