Searched refs:dd_csr (Results 1 – 5 of 5) sorted by relevance
208 DPRINTF(("en_put: txdma->dd_csr = %x\n",txdma->dd_csr)); in en_put()223 txdma->dd_csr = (turbo ? DMACSR_INITBUFTURBO : DMACSR_INITBUF) | in en_put()225 txdma->dd_csr = 0; in en_put()230 txdma->dd_csr = DMACSR_SETENABLE; in en_put()241 state = txdma->dd_csr & in en_put()249 txdma->dd_csr = DMACSR_RESET | DMACSR_CLRCOMPLETE; in en_put()292 DPRINTF(("en_get: rxdma->dd_csr = %x\n",rxdma->dd_csr)); in en_get()301 rxdma->dd_csr = 0; in en_get()302 rxdma->dd_csr = (turbo ? DMACSR_INITBUFTURBO : DMACSR_INITBUF) | in en_get()324 rxdma->dd_csr = DMACSR_SETENABLE | DMACSR_READ; in en_get()[all …]
79 dma->dd_csr = DMACSR_RESET; in scsi_init()372 dma->dd_csr = DMACSR_READ | DMACSR_RESET; in dma_start()375 dma->dd_csr = DMACSR_READ | DMACSR_SETENABLE; in dma_start()377 dma->dd_csr = 0; in dma_start()378 dma->dd_csr = DMACSR_INITBUF | DMACSR_READ | DMACSR_RESET; in dma_start()381 dma->dd_csr = DMACSR_READ | DMACSR_SETENABLE; in dma_start()401 state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE in dma_done()422 state = dma->dd_csr & (DMACSR_BUSEXC | DMACSR_COMPLETE in dma_done()429 dma->dd_csr = DMACSR_CLRCOMPLETE | DMACSR_RESET; in dma_done()
58 volatile uint32_t dd_csr; /* control & status register */ member
58 int dd_csr; /* control & status register */
899 u_long dd_csr; in nextdma_print() local916 dd_csr = nd_bsr4(DD_CSR); in nextdma_print()992 snprintb(sbuf, sizeof(sbuf), DMACSR_BITS, dd_csr); in nextdma_print()