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/mirbsd/src/gnu/usr.bin/binutils/gas/
Dm68k-parse.c170 enum m68k_register reg; member
1261 op->reg = yyvsp[0].reg;
1269 op->reg = yyvsp[0].reg;
1277 op->reg = yyvsp[0].reg;
1285 op->reg = yyvsp[0].reg;
1293 op->reg = yyvsp[0].reg;
1333 op->reg = yyvsp[-1].reg;
1341 op->reg = yyvsp[-2].reg;
1349 op->reg = yyvsp[-1].reg;
1356 op->reg = yyvsp[-1].reg;
[all …]
/mirbsd/src/gnu/usr.bin/binutils/gdb/
Duser-regs.c62 user_reg_read_ftype *read, struct user_reg *reg) in append_user_reg() argument
67 gdb_assert (reg != NULL); in append_user_reg()
68 reg->name = name; in append_user_reg()
69 reg->read = read; in append_user_reg()
70 reg->next = NULL; in append_user_reg()
71 (*regs->last) = reg; in append_user_reg()
94 struct user_reg *reg; in user_regs_init() local
97 for (reg = builtin_user_regs.first; reg != NULL; reg = reg->next) in user_regs_init()
98 append_user_reg (regs, reg->name, reg->read, in user_regs_init()
147 struct user_reg *reg; in user_reg_map_name_to_regnum() local
[all …]
Ddwarf2-frame.c106 struct dwarf2_frame_state_reg *reg; member
151 rs->reg = (struct dwarf2_frame_state_reg *) in dwarf2_frame_state_alloc_regs()
152 xrealloc (rs->reg, num_regs * size); in dwarf2_frame_state_alloc_regs()
155 memset (rs->reg + rs->num_regs, 0, (num_regs - rs->num_regs) * size); in dwarf2_frame_state_alloc_regs()
166 struct dwarf2_frame_state_reg *reg; in dwarf2_frame_state_copy_regs() local
168 reg = (struct dwarf2_frame_state_reg *) xmalloc (size); in dwarf2_frame_state_copy_regs()
169 memcpy (reg, rs->reg, size); in dwarf2_frame_state_copy_regs()
171 return reg; in dwarf2_frame_state_copy_regs()
183 xfree (rs->reg); in dwarf2_frame_state_free_regs()
197 xfree (fs->initial.reg); in dwarf2_frame_state_free()
[all …]
/mirbsd/src/sys/dev/pci/
Dif_vgevar.h98 #define CSR_WRITE_4(sc, reg, val) \ argument
99 bus_space_write_4(sc->vge_btag, sc->vge_bhandle, reg, val)
100 #define CSR_WRITE_2(sc, reg, val) \ argument
101 bus_space_write_2(sc->vge_btag, sc->vge_bhandle, reg, val)
102 #define CSR_WRITE_1(sc, reg, val) \ argument
103 bus_space_write_1(sc->vge_btag, sc->vge_bhandle, reg, val)
105 #define CSR_READ_4(sc, reg) \ argument
106 bus_space_read_4(sc->vge_btag, sc->vge_bhandle, reg)
107 #define CSR_READ_2(sc, reg) \ argument
108 bus_space_read_2(sc->vge_btag, sc->vge_bhandle, reg)
[all …]
Dpci_map.c58 nbsd_pci_io_find(pc, tag, reg, type, basep, sizep, flagsp) in nbsd_pci_io_find() argument
61 int reg;
70 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))
84 address = pci_conf_read(pc, tag, reg);
85 pci_conf_write(pc, tag, reg, 0xffffffff);
86 mask = pci_conf_read(pc, tag, reg);
87 pci_conf_write(pc, tag, reg, address);
115 nbsd_pci_mem_find(pc, tag, reg, type, basep, sizep, flagsp) in nbsd_pci_mem_find() argument
118 int reg;
130 if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3))
[all …]
Dagp_ali.c83 pcireg_t reg; in agp_ali_attach() local
119 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE); in agp_ali_attach()
120 reg = (reg & 0xff) | gatt->ag_physical; in agp_ali_attach()
121 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_ATTBASE, reg); in agp_ali_attach()
124 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL); in agp_ali_attach()
125 reg = (reg & ~0xff) | 0x10; in agp_ali_attach()
126 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL, reg); in agp_ali_attach()
136 pcireg_t reg;
144 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_ALI_TLBCTRL);
145 reg &= ~0xff;
[all …]
Dif_skreg.h76 #define SK_WIN(reg) (((reg) & SK_WIN_MASK) / SK_WIN_LEN) argument
79 #define SK_REG(reg) ((reg) & SK_REG_MASK) argument
106 #define SK_IF_READ_4(sc_if, skip, reg) \ argument
107 sk_win_read_4(sc_if->sk_softc, reg + \
109 #define SK_IF_READ_2(sc_if, skip, reg) \ argument
110 sk_win_read_2(sc_if->sk_softc, reg + \
112 #define SK_IF_READ_1(sc_if, skip, reg) \ argument
113 sk_win_read_1(sc_if->sk_softc, reg + \
116 #define SK_IF_WRITE_4(sc_if, skip, reg, val) \ argument
118 reg + ((sc_if->sk_port * (skip + 1)) * SK_WIN_LEN), val)
[all …]
Dsv.c205 sv_write (sc, reg, val) in sv_write() argument
207 u_int8_t reg, val;
210 bus_space_write_1(sc->sc_iot, sc->sc_ioh, reg, val);
214 sv_read (sc, reg) in sv_read() argument
216 u_int8_t reg;
219 return (bus_space_read_1(sc->sc_iot, sc->sc_ioh, reg));
223 sv_read_indirect (sc, reg) in sv_read_indirect() argument
225 u_int8_t reg;
232 iaddr |= (reg & SV_IADDR_MASK);
239 sv_write_indirect (sc, reg, val) in sv_write_indirect() argument
[all …]
Dagp_sis.c82 pcireg_t reg; in agp_sis_attach() local
122 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL); in agp_sis_attach()
123 reg |= (0x05 << 24) | 3; in agp_sis_attach()
124 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL, reg); in agp_sis_attach()
134 pcireg_t reg;
141 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL);
142 reg &= ~3;
143 reg &= 0x00ffffff;
144 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_SIS_WINCTRL, reg);
171 pcireg_t reg; in agp_sis_set_aperture() local
[all …]
Dagp_intel.c83 pcireg_t reg; in agp_intel_attach() local
128 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG); in agp_intel_attach()
129 reg &= ~(1 << 10); in agp_intel_attach()
130 reg |= (1 << 9); in agp_intel_attach()
131 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_NBXCFG, reg); in agp_intel_attach()
133 reg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_STS); in agp_intel_attach()
134 reg &= ~0x00ff0000; in agp_intel_attach()
135 reg |= (7 << 16); in agp_intel_attach()
136 pci_conf_write(sc->sc_pc, sc->sc_pcitag, AGP_INTEL_STS, reg); in agp_intel_attach()
146 pcireg_t reg;
[all …]
/mirbsd/src/sys/dev/ic/
Dvgavar.h72 static inline u_int8_t _vga_attr_read(vh, reg) in _vga_attr_read() argument
74 int reg;
81 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_ATC_INDEX, reg);
93 static inline void _vga_attr_write(vh, reg, val) in _vga_attr_write() argument
95 int reg;
101 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_ATC_INDEX, reg);
111 static inline u_int8_t _vga_ts_read(vh, reg) in _vga_ts_read() argument
113 int reg;
115 bus_space_write_1(vh->vh_iot, vh->vh_ioh_vga, VGA_TS_INDEX, reg);
119 static inline void _vga_ts_write(vh, reg, val) in _vga_ts_write() argument
[all …]
Dtropicreg.h62 #define RB_INB(sc, rb, reg) SR_INB(sc, (rb)+(reg)) argument
63 #define RB_INW(sc, rb, reg) SR_INW(sc, (rb)+(reg)) argument
66 #define ACA_RDB(sc, reg) MM_INB(sc, ((sc->sc_aca+(reg))|ACA_RW)) argument
67 #define ACA_RDW(sc, reg) MM_INW(sc, ((sc->sc_aca+(reg))|ACA_RW)) argument
68 #define ACA_OUTB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RW), (val)) argument
69 #define ACA_SETB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_SET), (val)) argument
70 #define ACA_RSTB(sc, reg, val) MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RST), (val)) argument
73 #define SSB_INB(sc, ssb, reg) SR_INB(sc, (ssb)+(reg)) argument
76 #define ARB_INB(sc, arb, reg) SR_INB(sc, (arb)+(reg)) argument
77 #define ARB_INW(sc, arb, reg) SR_INW(sc, (arb)+(reg)) argument
[all …]
Dtcic2var.h188 tcic_read_1(h, reg) in tcic_read_1() argument
190 int reg;
192 return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg));
197 tcic_read_2(h, reg) in tcic_read_2() argument
199 int reg;
201 return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg));
206 tcic_read_4(h, reg) in tcic_read_4() argument
208 int reg;
211 val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg);
212 val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16;
[all …]
Dmtd8xxreg.h200 #define CSR_READ_1(reg) bus_space_read_1(sc->sc_bust, sc->sc_bush, reg) argument
201 #define CSR_WRITE_1(reg, val) \ argument
202 bus_space_write_1(sc->sc_bust, sc->sc_bush, reg, val)
204 #define CSR_READ_2(reg) bus_space_read_2(sc->sc_bust, sc->sc_bush, reg) argument
205 #define CSR_WRITE_2(reg, vat) \ argument
206 bus_space_write_2(sc->sc_bust, sc->sc_bush, reg, val)
208 #define CSR_READ_4(reg) bus_space_read_4(sc->sc_bust, sc->sc_bush, reg) argument
209 #define CSR_WRITE_4(reg, val) \ argument
210 bus_space_write_4(sc->sc_bust, sc->sc_bush, reg, val)
212 #define CSR_SETBIT(reg, val) CSR_WRITE_4(reg, CSR_READ_4(reg) | (val)) argument
[all …]
Dtcic2.c323 int i, reg; local
338 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING;
339 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK);
340 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg);
341 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL;
342 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg);
343 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK);
344 reg |= TCIC_ILOCK_HOLD_CCLK;
345 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg);
358 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA);
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/mirbsd/src/gnu/usr.bin/binutils/gas/config/
Dm68k-parse.y98 enum m68k_register reg; member
105 %token <reg> DR AR FPR FPCR LPC ZAR ZDR LZPC CREG
110 %type <reg> zadr zdr apc zapc zpc optzapc optczapc
156 op->reg = $1;
161 op->reg = $1;
166 op->reg = $1;
171 op->reg = $1;
176 op->reg = $1;
209 op->reg = $2;
214 op->reg = $2;
[all …]
Dtc-mcore.c498 parse_reg (char * s, unsigned * reg) in parse_reg() argument
508 *reg = 10 + s[2] - '0'; in parse_reg()
514 *reg = s[1] - '0'; in parse_reg()
522 * reg = 0; in parse_reg()
554 parse_creg (char * s, unsigned * reg) in parse_creg() argument
566 *reg = 30 + s[3] - '0'; in parse_creg()
572 *reg = 20 + s[3] - '0'; in parse_creg()
578 *reg = 10 + s[3] - '0'; in parse_creg()
584 *reg = s[2] - '0'; in parse_creg()
603 *reg = cregs[i].crnum; in parse_creg()
[all …]
/mirbsd/src/sys/arch/i386/pci/
Dpci_bus_fixup.c55 pcireg_t reg; local
65 reg = pci_conf_read(pc, tag, PCI_ID_REG);
72 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
75 if (PCI_VENDOR(reg) == 0)
78 qd = pci_lookup_quirkdata(PCI_VENDOR(reg), PCI_PRODUCT(reg));
80 reg = pci_conf_read(pc, tag, PCI_BHLC_REG);
81 if (PCI_HDRTYPE_MULTIFN(reg) ||
90 reg = pci_conf_read(pc, tag, PCI_ID_REG);
93 if (PCI_VENDOR(reg) == PCI_VENDOR_INVALID)
96 if (PCI_VENDOR(reg) == 0)
[all …]
Dvia8231.c128 #define VIA8231_GET_TRIGGER_CNFG(reg, pirq) \ argument
129 ((reg & via8231_trigger_cnfg[pirq].mask) >> \
132 #define VIA8231_SET_TRIGGER_CNFG(reg, pirq, cfg) \ argument
133 reg = (reg & ~via8231_trigger_cnfg[pirq].mask) | \
137 #define VIA8231_GET_ROUTING_CNFG(reg, pirq) \ argument
138 (((reg) & via8231_routing_cnfg[pirq].mask) >> \
141 #define VIA8231_SET_ROUTING_CNFG(reg, pirq, cfg) \ argument
142 reg = (reg & ~via8231_routing_cnfg[pirq].mask) | \
193 int reg, val; local
198 reg = VIA8231_GET_ROUTING(ph);
[all …]
Dvia82c586.c106 #define VP3_TRIGGER(reg, pirq) (((reg) >> vp3_cfg_trigger_shift[(pirq)]) & \ argument
119 #define VP3_PIRQ(reg, pirq) (((reg) >> vp3_cfg_intr_shift[(pirq)]) & \ argument
130 pcireg_t reg; local
138 reg = pci_conf_read(pc, tag, VP3_CFG_KBDMISCCTRL12_REG);
139 reg |= VP3_CFG_MISCCTRL2_EISA4D04D1PORT_ENABLE <<
141 pci_conf_write(pc, tag, VP3_CFG_KBDMISCCTRL12_REG, reg);
169 pcireg_t reg; local
175 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, VP3_CFG_PIRQ_REG);
176 val = VP3_PIRQ(reg, clink);
190 pcireg_t reg; local
[all …]
Dopti82c700.c212 pcireg_t reg; local
218 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
219 val = (reg >> ofs) & FIRESTAR_CFG_PIRQ_MASK;
234 pcireg_t reg; local
242 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
243 reg &= ~(FIRESTAR_CFG_PIRQ_MASK << ofs);
244 reg |= (irq << ofs);
245 pci_conf_write(ph->ph_pc, ph->ph_tag, addrofs, reg);
257 pcireg_t reg; local
271 reg = pci_conf_read(ph->ph_pc, ph->ph_tag, addrofs);
[all …]
/mirbsd/src/sys/dev/sdmmc/
Dsdmmc_cis.c59 int reg; in sdmmc_read_cis() local
71 reg = (int)sdmmc_cisptr(sf); in sdmmc_read_cis()
72 if (reg < SD_IO_CIS_START || in sdmmc_read_cis()
73 reg >= (SD_IO_CIS_START+SD_IO_CIS_SIZE-16)) { in sdmmc_read_cis()
74 printf("%s: bad CIS ptr %#x\n", SDMMCDEVNAME(sf->sc), reg); in sdmmc_read_cis()
79 tplcode = sdmmc_io_read_1(sf, reg++); in sdmmc_read_cis()
80 tpllen = sdmmc_io_read_1(sf, reg++); in sdmmc_read_cis()
86 SDMMCDEVNAME(sf->sc), reg, tplcode, tpllen); in sdmmc_read_cis()
95 reg += tpllen; in sdmmc_read_cis()
98 cis->function = sdmmc_io_read_1(sf, reg); in sdmmc_read_cis()
[all …]
/mirbsd/src/sys/arch/sparc/dev/
Dz8530sc.c129 u_char *reg; local
146 reg = cs->cs_creg; /* current regs */
149 zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK);
152 zs_write_reg(cs, 4, reg[4]);
155 zs_write_reg(cs, 10, reg[10]);
158 zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE);
159 zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE);
162 zs_write_reg(cs, 6, reg[6]);
163 zs_write_reg(cs, 7, reg[7]);
174 zs_write_reg(cs, 2, reg[2]);
[all …]
/mirbsd/src/sys/dev/cardbus/
Dcardbus_map.c76 cardbus_io_find(cc, cf, tag, reg, type, basep, sizep, flagsp) in cardbus_io_find() argument
80 int reg;
90 if (reg == CARDBUS_ROM_REG) {
94 if(reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
109 address = cardbus_conf_read(cc, cf, tag, reg);
110 cardbus_conf_write(cc, cf, tag, reg, 0xffffffff);
111 mask = cardbus_conf_read(cc, cf, tag, reg);
112 cardbus_conf_write(cc, cf, tag, reg, address);
148 cardbus_mem_find(cc, cf, tag, reg, type, basep, sizep, flagsp) in cardbus_mem_find() argument
152 int reg;
[all …]
/mirbsd/src/sys/dev/pcmcia/
Dpcmcia_cis.c705 u_int reg, dtype, dspeed; local
707 reg = pcmcia_tuple_read_1(tuple, 0);
708 dtype = reg & PCMCIA_DTYPE_MASK;
709 dspeed = reg & PCMCIA_DSPEED_MASK;
870 u_int reg, rasz, rmsz, rfsz; local
873 reg = pcmcia_tuple_read_1(tuple, 0);
874 rasz = 1 + ((reg & PCMCIA_TPCC_RASZ_MASK) >>
876 rmsz = 1 + ((reg & PCMCIA_TPCC_RMSZ_MASK) >>
878 rfsz = ((reg & PCMCIA_TPCC_RFSZ_MASK) >>
933 u_int reg, reg2; local
[all …]

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