Searched refs:BA0READ4 (Results 1 – 2 of 2) sorted by relevance
| /mirbsd/src/sys/dev/pci/ |
| D | cs4281.c | 148 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) macro
401 intr = BA0READ4(sc, CS4281_HISR);
409 val = BA0READ4(sc, CS4281_HDSR0); /* clear intr condition */
411 val = BA0READ4(sc, CS4281_HDSR1); /* clear intr condition */
416 DPRINTF((" PB DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA0),
417 (int)BA0READ4(sc, CS4281_DCC0)));
435 val = BA0READ4(sc, CS4281_HDSR1);
437 DPRINTF((" CP DMA 0x%x(%d)", (int)BA0READ4(sc, CS4281_DCA1),
438 (int)BA0READ4(sc, CS4281_DCC1)));
594 BA0WRITE4(sc, CS4281_DCR0, BA0READ4(sc, CS4281_DCR0) | DCRn_MSK);
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| D | cs4280.c | 167 #define BA0READ4(sc, r) bus_space_read_4((sc)->ba0t, (sc)->ba0h, (r)) macro
323 BA0READ4(sc, CS4280_ACSDA);
339 while (!(BA0READ4(sc, CS4280_ACSTS) & ACSTS_VSTS)) {
347 *data = BA0READ4(sc, CS4280_ACSDA);
380 while ((BA0READ4(sc, CS4280_ACCTL) & ACCTL_DCV)) {
690 intr = BA0READ4(sc, CS4280_HISR);
801 BA0READ4(sc, CS4280_MIDSR)));
804 ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_RBE) == 0)) {
805 data = BA0READ4(sc, CS4280_MIDRP) & MIDRP_MASK;
816 if ((BA0READ4(sc, CS4280_MIDSR) & MIDSR_TBF) == 0) {
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