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/freebsd-9-stable/contrib/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td19 // The same integer registers are used for i32 and i64 values.
22 def : Pat<(i64 (anyext i32:$val)), (COPY_TO_REGCLASS $val, I64Regs)>;
23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
40 def : Pat<(i64 (zext i32:$val)), (SRLri $val, 0)>;
41 def : Pat<(i64 (sext i32:$val)), (SRAri $val, 0)>;
43 def : Pat<(i64 (and i64:$val, 0xffffffff)), (SRLri $val, 0)>;
44 def : Pat<(i64 (sext_inreg i64:$val, i32)), (SRAri $val, 0)>;
46 defm SLLX : F3_S<"sllx", 0b100101, 1, shl, i64, I64Regs>;
47 defm SRLX : F3_S<"srlx", 0b100110, 1, srl, i64, I64Regs>;
48 defm SRAX : F3_S<"srax", 0b100111, 1, sra, i64, I64Regs>;
[all …]
/freebsd-9-stable/contrib/llvm/patches/
Dpatch-r262261-llvm-r198157-sparc.diff34 @@ -141,32 +141,36 @@ def : Pat<(i64 imm:$val),
38 +defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
39 +defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
40 +defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
42 -def : Pat<(and i64:$a, i64:$b), (ANDrr $a, $b)>;
43 -def : Pat<(or i64:$a, i64:$b), (ORrr $a, $b)>;
44 -def : Pat<(xor i64:$a, i64:$b), (XORrr $a, $b)>;
48 + [(set i64:$dst, (and i64:$b, (not i64:$c)))]>;
52 + [(set i64:$dst, (or i64:$b, (not i64:$c)))]>;
56 + [(set i64:$dst, (not (xor i64:$b, i64:$c)))]>;
[all …]
Dpatch-r275633-llvm-r223171-fix-vectorizer.diff50 +target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
71 + %iprom = sext i32 %i to i64
72 + %b = getelementptr inbounds %struct.X* undef, i64 %iprom, i32 1
98 - %idxprom = sext i32 %i.0 to i64
101 + %idxprom = sext i32 %i.02 to i64
102 %arrayidx = getelementptr inbounds i32 addrspace(1)* %b, i64 %idxprom
105 - %idxprom1 = sext i32 %i.0 to i64
106 + %idxprom1 = sext i32 %i.02 to i64
107 %arrayidx2 = getelementptr inbounds i32 addrspace(1)* %a, i64 %idxprom1
134 - %idxprom = sext i32 %i.0 to i64
[all …]
Dpatch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff38 define i64 @f1(i64 %a, i64 %b) {
51 +define i64 @f() #0 {
57 + %y = alloca i64, align 8
58 + %z = alloca i64, align 8
59 + store i64 1, i64* %y, align 8
60 + store i64 11579764786944, i64* %z, align 8
61 + %0 = load i64* %y, align 8
62 + %1 = load i64* %z, align 8
63 + %sub = sub i64 %0, %1
64 + ret i64 %sub
[all …]
Dpatch-r262261-llvm-r198740-sparc.diff56 [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
60 - [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
63 + [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
69 [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
73 - [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
76 + [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
82 [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
86 - [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
89 + [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
Dpatch-r262261-llvm-r198286-sparc.diff68 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
92 + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
93 + setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
94 + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
95 + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
133 [(set i64:$rd, SETHIimm:$imm22)]>;
142 + [(set i64:$rd,
143 + (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
152 +def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
153 +def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
[all …]
Dpatch-r262261-llvm-r198910-sparc.diff297 define i64 @test1(i64 %X, i64 %Y) {
298 @@ -14,7 +14,7 @@ define i64 @test1(i64 %X, i64 %Y) {
306 define i64 @test2(i64 %X, i64 %Y) {
385 define i64 @ret2(i64 %a, i64 %b) {
386 ret i64 %b
387 @@ -15,7 +15,7 @@ define i64 @ret2(i64 %a, i64 %b) {
394 define i64 @shl_imm(i64 %a) {
395 %x = shl i64 %a, 7
396 @@ -26,7 +26,7 @@ define i64 @shl_imm(i64 %a) {
403 define i64 @sra_reg(i64 %a, i64 %b) {
[all …]
Dpatch-r262264-llvm-r200453-sparc.diff24 + [(set i64:$rd,
25 + (atomic_swap_64 iPTR:$addr, i64:$rs2))]>;
37 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
38 - setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
39 + setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal);
40 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
41 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
83 +define i64 @test_swap_i64(i64 %a, i64* %ptr) {
85 + %b = atomicrmw xchg i64* %ptr, i64 42 monotonic
86 + ret i64 %b
Dpatch-r262261-llvm-r199187-sparc.diff30 +target datalayout = "E-m:e-i64:64-n32:64-S128"
40 +define void @spill4(i64* nocapture %p) {
42 + %val0 = load i64* %p
43 + %cmp0 = icmp ult i64 %val0, 385672958347594845
44 + %cm80 = zext i1 %cmp0 to i64
45 + store i64 %cm80, i64* %p, align 8
47 + %arrayidx1 = getelementptr inbounds i64* %p, i64 1
48 + %val = load i64* %arrayidx1
49 + %cmp = icmp ult i64 %val, 385672958347594845
50 + %cm8 = select i1 %cmp, i64 10, i64 20
[all …]
Dpatch-r267981-llvm-r211435-fix-ppc-fctiduz.diff31 if (DstVT != MVT::i32 && DstVT != MVT::i64)
35 + if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget.hasFPCVT())
52 - %b.addr = alloca i64, align 4
53 - %conv = fptoui float %a to i64
57 - store i64 %conv, i64* %b.addr, align 4
71 - %b.addr = alloca i64, align 8
72 - %conv = fptoui double %a to i64
76 - store i64 %conv, i64* %b.addr, align 8
92 define void @sitofp_single_i64(i64 %a, float %b) nounwind ssp {
97 %conv = sitofp i64 %a to float
[all …]
Dpatch-r262261-llvm-r198145-sparc.diff31 +declare i64 @receive_fp128(i64 %a, ...)
39 +define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {
41 + %0 = call i64 (i64, ...)* @receive_fp128(i64 %a, fp128 %b)
42 + ret i64 %0
66 if (LocVT == MVT::i64 && Offset < 6*8)
102 - // Full register, just bitconvert into i64.
104 - IReg, MVT::i64, CCValAssign::BCvt);
106 + // Full register, just bitconvert into i64.
108 + IReg, MVT::i64, CCValAssign::BCvt);
125 + // SPARC does not support i128 natively. Lower it into two i64, see below.
[all …]
Dpatch-r262261-llvm-r200141-sparc.diff27 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
28 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
31 - setOperationAction(ISD::CTPOP, MVT::i64, Legal);
32 + setOperationAction(ISD::CTPOP, MVT::i64,
34 setOperationAction(ISD::CTTZ , MVT::i64, Expand);
35 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
36 setOperationAction(ISD::CTLZ , MVT::i64, Expand);
Dpatch-r262261-llvm-r198591-sparc.diff548 @@ -141,6 +141,7 @@ def : Pat<(i64 imm:$val),
553 defm ANDX : F3_12<"and", 0b000001, and, I64Regs, i64, i64imm>;
554 defm ORX : F3_12<"or", 0b000010, or, I64Regs, i64, i64imm>;
555 defm XORX : F3_12<"xor", 0b000011, xor, I64Regs, i64, i64imm>;
557 defm ADDX : F3_12<"add", 0b000000, add, I64Regs, i64, i64imm>;
558 defm SUBX : F3_12<"sub", 0b000100, sub, I64Regs, i64, i64imm>;
560 -def : Pat<(SPcmpicc i64:$a, i64:$b), (CMPrr $a, $b)>;
566 [(set i64:$rd,
567 (tlsadd i64:$rs1, i64:$rs2, tglobaltlsaddr:$sym))]>;
571 -def : Pat<(SPcmpicc i64:$a, (i64 simm13:$b)), (CMPri $a, (as_i32imm $b))>;
[all …]
Dpatch-r262265-llvm-r201718-sparc.diff32 setOperationAction(ISD::UMULO, MVT::i64, Custom);
33 setOperationAction(ISD::SMULO, MVT::i64, Custom);
35 + setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
36 + setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
37 + setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
/freebsd-9-stable/contrib/llvm/lib/Target/PowerPC/
DPPCInstr64Bit.td18 def s16imm64 : Operand<i64> {
23 def u16imm64 : Operand<i64> {
28 def s17imm64 : Operand<i64> {
43 def tlsreg : Operand<i64> {
47 def tlsgd : Operand<i64> {}
48 def tlscall : Operand<i64> {
128 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
142 [(PPCcall_nop (i64 imm:$func))]>;
158 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
160 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
[all …]
DPPCCallingConv.td25 // On PPC64, integer return values are always promoted to i64
26 CCIfType<[i32], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
29 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
46 // Only handle ints and floats. All ints are promoted to i64.
49 CCIfType<[i8], CCPromoteToType<i64>>,
50 CCIfType<[i16], CCPromoteToType<i64>>,
51 CCIfType<[i32], CCPromoteToType<i64>>,
52 CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
57 // All small ints are promoted to i64. Vector types, quadword ints,
61 CCIfType<[i8], CCPromoteToType<i64>>,
[all …]
/freebsd-9-stable/cddl/contrib/opensolaris/cmd/dtrace/test/tst/common/aggs/
Dtst.signedkeyspos.d98 @i64["cat", (long long)-2] = sum(-2);
99 @i64["bear", (long long)-2] = sum(-22);
100 @i64["dog", (long long)-2] = sum(-222);
101 @i64["cat", (long long)-1] = sum(-1);
102 @i64["bear", (long long)-1] = sum(-11);
103 @i64["dog", (long long)-1] = sum(-111);
104 @i64["cat", (long long)0] = sum(0);
105 @i64["bear", (long long)0] = sum(10);
106 @i64["dog", (long long)0] = sum(100);
107 @i64["cat", (long long)1] = sum(1);
[all …]
Dtst.signedkeys.d113 @i64[(long long)-2] = sum(-2);
114 @i64[(long long)-1] = sum(-1);
115 @i64[(long long)0] = sum(0);
116 @i64[(long long)1] = sum(1);
117 @i64[(long long)2] = sum(2);
/freebsd-9-stable/contrib/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td37 (OpNode (i64 DoubleRegs:$b), (i64 DoubleRegs:$c)))]>;
87 [SDTCisVT<0, i64>, SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
144 [(set (i64 DoubleRegs:$dst),
145 (i64 (HexagonWrapperCombineRR (i32 IntRegs:$src1),
164 [(set (i64 DoubleRegs:$dst),
165 (i64 (HexagonWrapperCombineII (i32 pat1:$src1), (i32 pat2:$src2))))]>;
524 [(set (i32 IntRegs:$dst), (i32 (trunc (ctlz (i64 DoubleRegs:$src1)))))]>;
528 [(set (i32 IntRegs:$dst), (i32 (trunc (cttz (i64 DoubleRegs:$src1)))))]>;
552 [(set (i64 DoubleRegs:$dst), (add (i64 DoubleRegs:$src1),
553 (i64 DoubleRegs:$src2)))]>;
[all …]
DHexagonIntrinsicsDerived.td15 (i64
21 (i64
22 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
24 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2),
27 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
28 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_hireg))),
29 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src2), subreg_loreg)),
30 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_hireg))),
33 (i64
34 (MPYU64 (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1), subreg_loreg)),
[all …]
DHexagonInstrInfoV3.td60 [(set (i64 DoubleRegs:$dst),
61 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
62 (i64 DoubleRegs:$src1))),
63 (i64 DoubleRegs:$src1),
64 (i64 DoubleRegs:$src2))))]>,
71 [(set (i64 DoubleRegs:$dst),
72 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
73 (i64 DoubleRegs:$src1))),
74 (i64 DoubleRegs:$src1),
75 (i64 DoubleRegs:$src2))))]>,
/freebsd-9-stable/contrib/llvm/lib/Target/SystemZ/
DSystemZOperands.td116 // These all create MVT::i64 nodes to ensure the value is not sign-extended
123 return CurDAG->getTargetConstant(Value, MVT::i64);
129 return CurDAG->getTargetConstant(Value, MVT::i64);
135 return CurDAG->getTargetConstant(Value, MVT::i64);
141 return CurDAG->getTargetConstant(Value, MVT::i64);
147 return CurDAG->getTargetConstant(Value, MVT::i64);
153 return CurDAG->getTargetConstant(Value, MVT::i64);
158 return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);
163 return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);
168 return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);
[all …]
DSystemZCallingConv.td19 // Promote i32 to i64 if it has an explicit extension type.
20 CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
27 CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D]>>,
45 // Promote i32 to i64 if it has an explicit extension type.
49 CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
51 // Force long double values to the stack and pass i64 pointers to them.
52 CCIfType<[f128], CCPassIndirect<i64>>,
57 CCIfType<[i64], CCAssignToReg<[R2D, R3D, R4D, R5D, R6D]>>,
64 CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>
/freebsd-9-stable/sys/boot/ficl/
Dmath64.h58 void i64Push(FICL_STACK *pStack, DPINT i64);
75 #define i64Extend(i64) (i64).hi = ((i64).lo < 0) ? -1L : 0 argument
76 #define m64CastIU(i64) (*(DPUNS *)(&(i64))) argument
/freebsd-9-stable/contrib/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td110 SDTCisVT<3, i64>,
111 SDTCisVT<4, i64>]>;
117 SDTCisVT<3, i64>]>;
125 def SDTA64BFX : SDTypeProfile<1, 3, [SDTCisVT<2, i64>, SDTCisVT<3, i64>]>;
257 def _operand : Operand<i64>,
258 ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
280 def LSL_extoperand : Operand<i64> {
287 // legal i64 and i32 types. We'll wrap the various variants up in a
300 let uxtx = (i64 $Rm);
305 let sxtx = (i64 $Rm);
[all …]

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