Lines Matching refs:i64
68 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom);
92 + setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal);
93 + setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Expand);
94 + setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom);
95 + setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
133 [(set i64:$rd, SETHIimm:$imm22)]>;
142 + [(set i64:$rd,
143 + (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>;
152 +def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>;
153 +def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>;
156 +def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>;
157 +def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>;
194 +define i64 @test_atomic_i64(i64* %ptr1, i64* %ptr2, i64* %ptr3) {
196 + %0 = load atomic i64* %ptr1 acquire, align 8
197 + %1 = load atomic i64* %ptr2 acquire, align 8
198 + %2 = add i64 %0, %1
199 + store atomic i64 %2, i64* %ptr3 release, align 8
200 + ret i64 %2
217 +define i64 @test_cmpxchg_i64(i64 %a, i64* %ptr) {
219 + %b = cmpxchg i64* %ptr, i64 %a, i64 123 monotonic
220 + ret i64 %b