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Searched refs:div_mask (Results 1 – 5 of 5) sorted by relevance

/freebsd-14-stable/sys/arm/freescale/vybrid/
HDvf_ccm.c157 uint32_t div_mask; member
169 .div_mask = IPG_CLK_DIV_MASK,
193 .div_mask = PLL4_CLK_DIV_MASK,
205 .div_mask = SAI3_DIV_MASK,
217 .div_mask = CKO1_DIV_MASK,
229 .div_mask = ESDHC0_DIV_M,
241 .div_mask = ESDHC1_DIV_M,
253 .div_mask = 0,
265 .div_mask = 0x7,
277 .div_mask = 0,
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/freebsd-14-stable/sys/arm64/rockchip/clk/
HDrk_clk_composite.c49 uint32_t div_mask; member
182 div = ((reg & sc->div_mask) >> sc->div_shift); in rk_clk_composite_recalc()
205 for (div_reg = 0; div_reg <= ((sc->div_mask >> sc->div_shift) + 1); in rk_clk_composite_find_best()
279 dprintf(" div_mask: 0x%X, div_shift: %d\n", sc->div_mask, in rk_clk_composite_set_freq()
284 val |= sc->div_mask << RK_CLK_COMPOSITE_MASK_SHIFT; in rk_clk_composite_set_freq()
328 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_composite_register()
HDrk_clk_armclk.c47 uint32_t div_mask; member
133 div = ((reg & sc->div_mask) >> sc->div_shift) + 1; in rk_clk_armclk_recalc()
195 val |= sc->div_mask << RK_ARMCLK_WRITE_MASK_SHIFT; in rk_clk_armclk_set_freq()
240 sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; in rk_clk_armclk_register()
/freebsd-14-stable/sys/arm/nvidia/tegra124/
HDtegra124_clk_per.c64 uint32_t div_mask; member
526 uint32_t div_mask; member
566 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
662 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
686 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()
/freebsd-14-stable/sys/arm64/nvidia/tegra210/
HDtegra210_clk_per.c59 uint32_t div_mask; member
639 uint32_t div_mask; member
679 sc->divider = (reg & sc->div_mask) + 2; in periph_init()
776 MD4(sc, sc->base_reg, sc->div_mask, in periph_set_freq()
800 sc->div_mask = (1 <<clkdef->div_width) - 1; in periph_register()