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Searched refs:v1i64 (Results 1 – 25 of 28) sorted by relevance

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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMCallingConv.td33 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
74 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
94 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
111 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
168 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
186 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
213 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
236 CCIfType<[v1i64, v2i32, v4i16, v4f16, v4bf16, v8i8, v2f32], CCBitConvertToType<f64>>,
DARMInstrNEON.td1098 def : Pat<(insert_subvector undef, (v1i64 DPR:$src), (i32 0)),
3535 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3537 v1i64, v1i64, OpNode, Commutable>;
3643 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3645 v1i64, v1i64, IntOp, Commutable>;
3657 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3659 v1i64, v1i64, IntOp>;
3967 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3990 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
4021 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
[all …]
DARMScheduleA57.td1120 "VSLI(v8i8|v4i16|v2i32|v1i64)", "VSRI(v8i8|v4i16|v2i32|v1i64)")>;
1128 "VSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1137 "VQRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)", "VQSHL(s|u)(v8i8|v4i16|v2i32|v1i64)",
1138 "VRSHL(s|u)(v8i8|v4i16|v2i32|v1i64)")>;
1213 "VMOV(v8i8|v16i8|v4i16|v8i16|v2i32|v4i32|v1i64|v2i64|v2f32|v4f32)",
DARMRegisterInfo.td432 def DPR : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
453 def DPR_VFP2 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
460 def DPR_8 : RegisterClass<"ARM", [f64, v8i8, v4i16, v2i32, v1i64, v2f32, v4f16, v4bf16], 64,
DARMTargetTransformInfo.cpp1281 { ISD::SDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1282 { ISD::UDIV, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1283 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
1284 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
DARMScheduleR52.td775 (instregex "(VADD|VSUB)(v8i8|v4i16|v2i32|v1i64)")>;
819 def : InstRW<[R52WriteFPALU_F5, R52Read_F1], (instregex "VQABS(v8i8|v4i16|v2i32|v1i64)")>;
822 (instregex "(VQADD|VQSUB)(u|s)(v8i8|v4i16|v2i32|v1i64)")>;
DARMISelLowering.cpp207 VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
798 addDRTypeForNEON(MVT::v1i64); in ARMTargetLowering()
891 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in ARMTargetLowering()
924 setOperationAction(ISD::CTPOP, MVT::v1i64, Custom); in ARMTargetLowering()
927 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in ARMTargetLowering()
934 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in ARMTargetLowering()
944 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v1i64, Custom); in ARMTargetLowering()
1592 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: in findRepresentativeClass()
5895 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; in LowerFCOPYSIGN()
5909 Tmp1 = DAG.getNode(ARMISD::VSHRuIMM, dl, MVT::v1i64, in LowerFCOPYSIGN()
[all …]
DARMISelDAGToDAG.cpp2131 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVLD()
2276 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVST()
2989 case MVT::v1i64: OpcodeIndex = 3; break; in SelectVLDDup()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp3617 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3644 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3671 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3698 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3725 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3752 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3779 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3806 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3833 } else if (VT == MVT::v1i64 || VT == MVT::v1f64) { in Select()
3853 } else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 || in Select()
[all …]
DAArch64SchedA57.td349 // D form - v1i8, v1i16, v1i32, v1i64
381 …ite_5cyc_1W_Mul_Forward], (instregex "^MUL(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
383 …te_5cyc_1W], (instregex "^(PMUL|SQR?DMULH)(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)(_indexed)?$")>;
409 def : InstRW<[A57Write_3cyc_1W], (instregex "^PMULL(v1i64|v2i64)")>;
425 def : InstRW<[A57Write_4cyc_1X], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2…
438 // D form - v1i32, v1i64
453 …yc_1V], (instregex "^(FACGE|FACGT|FCMEQ|FCMGE|FCMGT|FCMLE|FCMLT)(v2f32|32|64|v1i32|v2i32|v1i64)")>;
460 …InstRW<[A57Write_5cyc_1V], (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
491 def : InstRW<[A57Write_5cyc_1V_FP_Forward], (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
505 def : InstRW<[A57WriteFPVMAD, A57ReadFPVMA5], (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
[all …]
DAArch64SchedFalkorDetails.td591 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64|v2i32)rz$")>;
598 def : InstRW<[FalkorWr_1VXVY_4cyc], (instregex "^FCVT(N|M|P|Z|A)(S|U)(v1i32|v1i64|v2f32)$")>;
658 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^ADD(v1i64|v2i32|v4i16|v8i8)$")>;
662 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^NEG(v1i64|v2i32|v4i16|v8i8)$")>;
663 def : InstRW<[FalkorWr_1VXVY_1cyc], (instregex "^SUB(v1i64|v2i32|v4i16|v8i8)$")>;
669 …XVY_2cyc], (instregex "^((S|U)?(MAX|MIN)P?|ABS|ADDP|CM(EQ|GE|HS|GT|HI))(v1i64|v2i32|v4i16|v8i8)$…
670 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|GE|HS|GT|HI)(v1i64|v2i32|v4i16|v8i8)$")>;
671 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CM(EQ|LE|GE|GT|LT)(v1i64|v2i32|v4i16|v8i8)rz$")>;
672 def : InstRW<[FalkorWr_1VXVY_2cyc], (instregex "^CMTST(v1i64|v2i32|v4i16|v8i8)$")>;
681 def : InstRW<[FalkorWr_1VXVY_3cyc], (instregex "^(S|U)QADD(v1i8|v1i16|v2i16|v1i32|v1i64|v2i32|v4i…
[all …]
DAArch64InstrInfo.td2465 def : Pat <(v1i64 (scalar_to_vector (i64
2470 def : Pat <(v1i64 (scalar_to_vector (i64
2498 defm : VecROLoadPat<ro64, v1i64, LDRDroW, LDRDroX>;
2625 def : Pat <(v1i64 (scalar_to_vector (i64
2651 def : Pat<(v1i64 (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset))),
2837 def : Pat<(v1i64 (load (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
3174 defm : VecROStorePat<ro64, v1i64, FPR64, STRDroW, STRDroX>;
3256 def : Pat<(store (v1i64 FPR64:$Rt),
3401 def : Pat<(store (v1i64 FPR64:$Rt), (am_unscaled64 GPR64sp:$Rn, simm9:$offset)),
3551 def : Pat<(pre_store (v1i64 FPR64:$Rt), GPR64sp:$addr, simm9:$off),
[all …]
DAArch64CallingConvention.td112 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
121 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
156 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
238 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
255 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8, v4f16, v4bf16],
276 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
298 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32, v4f16, v4bf16],
360 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
DAArch64SchedKryoDetails.td147 (instregex "(S|U)CVTF(v1i32|v2i32|v1i64|v2f32|d|s)(_shift)?")>;
213 (instregex "(S|U|SU|US)QADD(v1i8|v1i16|v2i16|v1i32|v1i64)")>;
231 (instregex "(S|U)(QSHL|RSHL|QRSHL)(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32)$")>;
261 (instregex "(S|U)QSUB(v8i8|v4i16|v2i32|v1i64|v1i32|v1i16|v1i8)")>;
285 (instregex "(S|U)SHL(d|v8i8|v4i16|v2i32|v1i64)$")>;
375 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
513 (instregex "CM(EQ|GE|HS|GT|HI|TST)(v8i8|v4i16|v2i32|v1i64)$")>;
525 (instregex "CM(EQ|LE|GE|GT|LT)(v8i8|v4i16|v2i32|v1i64)rz$")>;
693 (instregex "FCM(EQ|LE|GE|GT|LT)(v1i32|v1i64)rz")>;
735 (instregex "FCVT((A|N|M|P)(S|U)|Z(S|U)_Int)(v1i32|v1i64|v2f32)$")>;
[all …]
DAArch64SchedTSV110.td523 // D form - v1i8, v1i16, v1i32, v1i64
553 …0Wr_4cyc_1FSU1], (instregex "^(MUL|ML[AS]|SQR?D(MULH))(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)")>;
560 def : InstRW<[TSV110Wr_2cyc_1FSU1], (instregex "^PMULL(v1i64|v2i64)")>;
574 def : InstRW<[TSV110Wr_4cyc_1FSU1], (instregex "^[SU][QR]{1,2}SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16…
601 // D form - v1i32, v1i64
DAArch64InstrFormats.td5373 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
5374 (v1i64 V64:$RHS))),
5600 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
5631 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
5632 (v1i64 V64:$RHS))),
5824 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
5850 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
6403 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
6793 def v1i64 : BaseSIMDThreeScalar<U, 0b111, opc, FPR64, asm,
6794 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
[all …]
DAArch64SchedThunderX2T99.td1275 def : InstRW<[THX2T99Write_5Cyc_F01], (instregex "^PMULL(v1i64|v2i64)")>;
1307 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1336 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1343 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
1422 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1459 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1469 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64SchedThunderX3T110.td1382 def : InstRW<[THX3T110Write_5Cyc_F0123], (instregex "^PMULL(v1i64|v2i64)")>;
1414 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1443 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1450 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
1529 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1567 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1578 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64ISelLowering.cpp271 addDRTypeForNEON(MVT::v1i64); in AArch64TargetLowering()
994 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
995 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); in AArch64TargetLowering()
996 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
997 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
1000 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in AArch64TargetLowering()
1035 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in AArch64TargetLowering()
1041 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1233 MVT::v2i32, MVT::v4i32, MVT::v1i64, MVT::v2i64}) { in AArch64TargetLowering()
1332 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
[all …]
DAArch64SchedA64FX.td1650 def : InstRW<[A64FXWrite_8Cyc_GI03], (instregex "^PMULL(v1i64|v2i64)")>;
1682 "(v8i8|v4i16|v2i32|v1i8|v1i16|v1i32|v1i64)" #
1723 "(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
1730 (instregex "(ADD|SUB)(v8i8|v4i16|v2i32|v1i64)")>;
1814 (instregex "^[FVSU]CVT([AMNPZ][SU])?(_Int)?(v2f32|v1i32|v2i32|v1i64)")>;
1851 (instregex "^FMULX?(v2f32|v1i32|v2i32|v1i64|32|64)")>;
1861 (instregex "^FML[AS](v2f32|v1i32|v2i32|v1i64)")>;
DAArch64RegisterInfo.td445 v1i64, v4f16, v4bf16],
448 [v8i8, v4i16, v2i32, v1i64, v4f16, v4bf16, v2f32,
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h117 v1i64 = 64, // 1 x i64 enumerator
401 SimpleTy == MVT::v1i64 || SimpleTy == MVT::v4f16 || in is64BitVector()
598 case v1i64: in getVectorElementType()
829 case v1i64: in getVectorMinNumElements()
929 case v1i64: in getSizeInBits()
1239 if (NumElements == 1) return MVT::v1i64; in getVectorVT()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td90 def v1i64 : ValueType<64, 64>; // 1 x i64 vector value
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp305 case MVT::v1i64: in getTypeForEVT()
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp132 case MVT::v1i64: return "MVT::v1i64"; in getEnumName()

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