Lines Matching refs:v1i64

271     addDRTypeForNEON(MVT::v1i64);  in AArch64TargetLowering()
994 setOperationAction(ISD::FP_TO_SINT, MVT::v1i64, Expand); in AArch64TargetLowering()
995 setOperationAction(ISD::FP_TO_UINT, MVT::v1i64, Expand); in AArch64TargetLowering()
996 setOperationAction(ISD::SINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
997 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
1000 setOperationAction(ISD::MUL, MVT::v1i64, Expand); in AArch64TargetLowering()
1035 setOperationAction(ISD::CTLZ, MVT::v1i64, Expand); in AArch64TargetLowering()
1041 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1233 MVT::v2i32, MVT::v4i32, MVT::v1i64, MVT::v2i64}) { in AArch64TargetLowering()
1332 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1333 setOperationAction(ISD::CTLZ, MVT::v1i64, Custom); in AArch64TargetLowering()
1335 setOperationAction(ISD::CTTZ, MVT::v1i64, Custom); in AArch64TargetLowering()
1336 setOperationAction(ISD::MUL, MVT::v1i64, Custom); in AArch64TargetLowering()
1338 setOperationAction(ISD::MULHS, MVT::v1i64, Custom); in AArch64TargetLowering()
1340 setOperationAction(ISD::MULHU, MVT::v1i64, Custom); in AArch64TargetLowering()
1348 setOperationAction(ISD::SDIV, MVT::v1i64, Custom); in AArch64TargetLowering()
1350 setOperationAction(ISD::SMAX, MVT::v1i64, Custom); in AArch64TargetLowering()
1352 setOperationAction(ISD::SMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1360 setOperationAction(ISD::UDIV, MVT::v1i64, Custom); in AArch64TargetLowering()
1362 setOperationAction(ISD::UMAX, MVT::v1i64, Custom); in AArch64TargetLowering()
1364 setOperationAction(ISD::UMIN, MVT::v1i64, Custom); in AArch64TargetLowering()
1461 if (!VT.isFloatingPoint() && VT != MVT::v2i64 && VT != MVT::v1i64) in addTypeForNEON()
3752 bool OverrideNEON = VT == MVT::v2i64 || VT == MVT::v1i64; in LowerMUL()
3874 SDValue Result = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, in LowerINTRINSIC_WO_CHAIN()
3876 Result = DAG.getNode(ISD::ABS, dl, MVT::v1i64, Result); in LowerINTRINSIC_WO_CHAIN()
7112 assert((VT == MVT::v1i64 || VT == MVT::v2i64 || VT == MVT::v2i32 || in LowerCTPOP()
7176 case MVT::v1i64: { in LowerBitreverse()
10427 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16 && in LowerINSERT_VECTOR_ELT()
10477 VT != MVT::v1i64 && VT != MVT::v2f32 && VT != MVT::v4f16 && in LowerEXTRACT_VECTOR_ELT()