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Searched refs:v1i1 (Results 1 – 12 of 12) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/X86/
DX86CallingConv.td81 // Promote i1/i8/i16/v1i1 arguments to i32.
82 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
155 // Promote i1, v1i1, v8i1 arguments to i8.
156 CCIfType<[i1, v1i1, v8i1], CCPromoteToType<i8>>,
216 CCIfType<[v1i1], CCPromoteToType<i8>>,
393 CCIfType<[v1i1], CCPromoteToType<i8>>,
508 // Promote i1/i8/i16/v1i1 arguments to i32.
509 CCIfType<[i1, i8, i16, v1i1], CCPromoteToType<i32>>,
618 // Promote i1/v1i1 arguments to i8.
619 CCIfType<[i1, v1i1], CCPromoteToType<i8>>,
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DX86InstrVecCompiler.td167 def maskzeroupperv1i1 : maskzeroupper<v1i1, VK1>;
254 (v1i1 VK1:$mask), (iPTR 0))),
282 (v1i1 VK1:$mask), (iPTR 0))),
332 (v1i1 VK1:$mask), (iPTR 0))),
345 (v1i1 VK1:$mask), (iPTR 0))),
DX86RegisterInfo.td609 def VK1 : RegisterClass<"X86", [v1i1], 16, (sequence "K%u", 0, 7)> {let Size = 16;}
627 def VK1WM : RegisterClass<"X86", [v1i1], 16, (sub VK1, K0)> {let Size = 16;}
DX86InstrFragmentsSIMD.td303 SDTypeProfile<1, 3, [SDTCisVT<1, v1i1>,
495 SDTypeProfile<1, 2, [SDTCisVT<0, v1i1>,
DX86InstrAVX512.td164 def v1i1_info : X86KVectorVTInfo<VK1, VK1WM, v1i1>;
2583 def : Pat<(v1i1 (X86cmpms (loadf64 addr:$src2), FR64X:$src1,
2587 def : Pat<(v1i1 (X86cmpms (loadf32 addr:$src2), FR32X:$src1,
2857 def : Pat<(v1i1 (load addr:$src)),
2892 defm : operation_gpr_mask_copy_lowering<VK1, v1i1>;
2901 (v1i1 (scalar_to_vector GR8:$src)), (iPTR 0)),
3283 def : Pat<(v1i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK1)>;
3287 def : Pat<(v1i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK1)>;
3299 defm : operation_subvector_mask_lowering<VK1, v1i1, VK2, v2i1>;
3300 defm : operation_subvector_mask_lowering<VK1, v1i1, VK4, v4i1>;
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DX86ISelLowering.cpp1448 addRegisterClass(MVT::v1i1, &X86::VK1RegClass); in X86TargetLowering()
1454 setOperationAction(ISD::SELECT, MVT::v1i1, Custom); in X86TargetLowering()
1455 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom); in X86TargetLowering()
1456 setOperationAction(ISD::BUILD_VECTOR, MVT::v1i1, Custom); in X86TargetLowering()
1473 setOperationAction(ISD::LOAD, MVT::v1i1, Custom); in X86TargetLowering()
1478 setOperationAction(ISD::STORE, MVT::v1i1, Custom); in X86TargetLowering()
1491 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 }) in X86TargetLowering()
1509 for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 }) in X86TargetLowering()
2629 if (ValVT == MVT::v1i1) in lowerMasksToReg()
3005 if (ValVT == MVT::v1i1) in lowerRegToMasks()
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DX86InstrCompiler.td575 defm _VK1 : CMOVrr_PSEUDO<VK1, v1i1>;
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Support/
DMachineValueType.h64 v1i1 = 15, // 1 x i1 enumerator
130 FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
185 FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
257 FIRST_VECTOR_VALUETYPE = v1i1,
523 case v1i1: in getVectorElementType()
825 case v1i1: in getVectorMinNumElements()
880 case v1i1: return TypeSize::Fixed(1); in getSizeInBits()
1182 if (NumElements == 1) return MVT::v1i1; in getVectorVT()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DValueTypes.td37 def v1i1 : ValueType<1, 15>; // 1 x i1 vector value
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DValueTypes.cpp207 case MVT::v1i1: in getTypeForEVT()
/freebsd-12-stable/contrib/llvm-project/llvm/utils/TableGen/
DCodeGenTarget.cpp83 case MVT::v1i1: return "MVT::v1i1"; in getEnumName()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorTypes.cpp767 assert(N->getValueType(0) == MVT::v1i1 && "Expected v1i1 type"); in ScalarizeVecOp_VSETCC()