1448     addRegisterClass(MVT::v1i1,   &X86::VK1RegClass);  in X86TargetLowering()
1454     setOperationAction(ISD::SELECT,             MVT::v1i1, Custom);  in X86TargetLowering()
1455     setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v1i1, Custom);  in X86TargetLowering()
1456     setOperationAction(ISD::BUILD_VECTOR,       MVT::v1i1, Custom);  in X86TargetLowering()
1473       setOperationAction(ISD::LOAD, MVT::v1i1, Custom);  in X86TargetLowering()
1478       setOperationAction(ISD::STORE, MVT::v1i1, Custom);  in X86TargetLowering()
1491     for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v16i1 })  in X86TargetLowering()
1509     for (auto VT : { MVT::v1i1, MVT::v2i1, MVT::v4i1, MVT::v8i1 })  in X86TargetLowering()
2629   if (ValVT == MVT::v1i1)  in lowerMasksToReg()
3005   if (ValVT == MVT::v1i1)  in lowerRegToMasks()
3006     return DAG.getNode(ISD::SCALAR_TO_VECTOR, Dl, MVT::v1i1, ValReturned);  in lowerRegToMasks()
3689         else if (RegVT == MVT::v1i1)  in LowerFormalArguments()
18946   SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i1, Elt);  in InsertBitToMaskVector()
23806           DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CondOp0, CondOp1,  in LowerSELECT()
23853     SDValue Cmp = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1, Cond);  in LowerSELECT()
25121   SDValue IMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v1i1,  in getScalarMaskingNode()
25570       SDValue FPclass = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Imm);  in LowerINTRINSIC_WO_CHAIN()
25610           Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::v1i1, Src1, Src2, CC, Sae);  in LowerINTRINSIC_WO_CHAIN()
25616         Cmp = DAG.getNode(IntrData->Opc0, dl, MVT::v1i1, Src1, Src2, CC);  in LowerINTRINSIC_WO_CHAIN()
25672         FCmp = DAG.getNode(X86ISD::FSETCCM, dl, MVT::v1i1, LHS, RHS,  in LowerINTRINSIC_WO_CHAIN()
25675         FCmp = DAG.getNode(X86ISD::FSETCCM_SAE, dl, MVT::v1i1, LHS, RHS,  in LowerINTRINSIC_WO_CHAIN()
44362                 DAG.getNode(X86ISD::FSETCCM, DL, MVT::v1i1, CMP00, CMP01,  in combineCompareEqual()
46166   if (VT == MVT::v1i1 && VT == StVT && Subtarget.hasAVX512() &&  in combineStore()
46179   if ((VT == MVT::v1i1 || VT == MVT::v2i1 || VT == MVT::v4i1) && VT == StVT &&  in combineStore()
50782   if (VT == MVT::v1i1 && Src.getOpcode() == ISD::AND && Src.hasOneUse())  in combineScalarToVector()
50785         return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v1i1,  in combineScalarToVector()
50789   if (VT == MVT::v1i1 && Src.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&  in combineScalarToVector()