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Searched refs:mfspr (Results 1 – 25 of 42) sorted by relevance

12

/freebsd-12-stable/sys/powerpc/aim/
Dmp_cpudep.c152 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
160 ccr = mfspr(SPR_L2CR); in mpc74xx_l2_enable()
174 ccr = mfspr(SPR_L3CR); in mpc745x_l3_enable()
186 while (mfspr(SPR_L3CR) & L3CR_L3I) in mpc745x_l3_enable()
206 hid = mfspr(SPR_HID0); in mpc74xx_l1d_enable()
224 hid = mfspr(SPR_HID0); in mpc74xx_l1i_enable()
249 bsp_state[0] = mfspr(SPR_HID0); in cpudep_save_config()
250 bsp_state[1] = mfspr(SPR_HID1); in cpudep_save_config()
251 bsp_state[2] = mfspr(SPR_HID4); in cpudep_save_config()
252 bsp_state[3] = mfspr(SPR_HID5); in cpudep_save_config()
[all …]
Daim_machdep.c207 scratch = mfspr(SPR_HID5); in aim_early_init()
562 msscr0 = mfspr(SPR_MSSCR0); in flush_disable_caches()
575 mtspr(SPR_LDSTCR, mfspr(SPR_LDSTCR) | 0xFF); in flush_disable_caches()
606 cache_reg = mfspr(SPR_L2CR); in flush_disable_caches()
612 while (mfspr(SPR_L2CR) & L2CR_L2HWF) in flush_disable_caches()
620 while (mfspr(SPR_L2CR) & L2CR_L2I) in flush_disable_caches()
625 cache_reg = mfspr(SPR_L3CR); in flush_disable_caches()
631 while (mfspr(SPR_L3CR) & L3CR_L3HWF) in flush_disable_caches()
639 while (mfspr(SPR_L3CR) & L3CR_L3I) in flush_disable_caches()
644 mtspr(SPR_HID0, mfspr(SPR_HID0) & ~HID0_DCE); in flush_disable_caches()
[all …]
Dtrap_subr32.S400 mfspr %r2, SPR_HASH1 /* get first pointer */
403 mfspr %r3, SPR_ICMP /* get first compare value */
418 mfspr %r0, SPR_IMISS /* get the miss address for the tlbli */
419 mfspr %r3, SPR_SRR1 /* get the saved cr0 bits */
431 mfspr %r2, SPR_HASH2 /* get the second pointer */
439 mfspr %r3, SPR_SRR1 /* get srr1 */
445 mfspr %r3, SPR_SRR1 /* get srr1 */
465 mfspr %r2, SPR_HASH1 /* get first pointer */
468 mfspr %r3, SPR_DCMP /* get first compare value */
481 mfspr %r0, SPR_DMISS /* get the miss address for the tlbld */
[all …]
Dlocore.S14 mfspr %r3, 0
/freebsd-12-stable/sys/powerpc/booke/
Dmachdep_e500.c67 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
73 csr = mfspr(SPR_L1CSR0); in booke_enable_l1_cache()
79 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
85 csr = mfspr(SPR_L1CSR1); in booke_enable_l1_cache()
99 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
105 csr = mfspr(SPR_L2CSR0); in booke_enable_l2_cache()
118 csr = mfspr(SPR_BUCSR); in booke_enable_bpred()
Dlocore.S46 mfspr r, SPR_SPRG8
626 mfspr %r17, SPR_PID0
631 mfspr %r17, SPR_MAS0
635 mfspr %r17, SPR_MAS1
688 mfspr %r5, SPR_MAS1
713 mfspr %r3, SPR_TLB1CFG /* Get number of entries */
721 mfspr %r5, SPR_MAS1
800 mfspr %r3, SPR_L1CSR0
806 1: mfspr %r3, SPR_L1CSR0
813 mfspr %r3, SPR_L1CSR0
[all …]
Dtrap_subr.S127 mfspr %r30, isrr0; \
128 mfspr %r31, isrr1; /* MSR at interrupt time */ \
132 mfspr %r1, sprg_sp; /* Restore SP */ \
150 mfspr %r30, isrr0; \
151 mfspr %r31, isrr1; /* MSR at interrupt time */ \
154 mfspr %r30, SPR_SRR0; \
155 mfspr %r31, SPR_SRR1; /* MSR at interrupt time */ \
159 mfspr %r1, sprg_sp; /* Restore SP */ \
260 mfspr %r31, sprg_sp; /* get saved SP */ \
287 mfspr %r3, SPR_DBCR0; \
[all …]
Dmp_cpudep.c59 csr = mfspr(SPR_L1CSR0); in cpudep_ap_bootstrap()
65 csr = mfspr(SPR_L1CSR1); in cpudep_ap_bootstrap()
Dbooke_machdep.c275 mtspr(SPR_EPCR, mfspr(SPR_EPCR) | EPCR_ICM); in ivor_setup()
441 r = mfspr(SPR_DBCR0); in kdb_cpu_clear_singlestep()
451 r = mfspr(SPR_DBCR0); in kdb_cpu_set_singlestep()
Dpmap.c552 tlb0_cfg = mfspr(SPR_TLB0CFG); in tlb0_get_tlbconf()
564 tlb1_cfg = mfspr(SPR_TLB1CFG); in tlb1_get_tlbconf()
2760 td->td_pcb->pcb_cpu.booke.dbcr0 = mfspr(SPR_DBCR0); in mmu_booke_deactivate()
3893 entry->mas1 = mfspr(SPR_MAS1); in tlb1_read_entry()
3894 entry->mas2 = mfspr(SPR_MAS2); in tlb1_read_entry()
3895 entry->mas3 = mfspr(SPR_MAS3); in tlb1_read_entry()
3902 entry->mas7 = mfspr(SPR_MAS7); in tlb1_read_entry()
4170 mas1 = mfspr(SPR_MAS1); in tlb1_init()
4171 mas2 = mfspr(SPR_MAS2); in tlb1_init()
4172 mas3 = mfspr(SPR_MAS3); in tlb1_init()
[all …]
Dspe.c88 pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR); in save_vec_int()
125 pcb->pcb_vec.vscr = mfspr(SPR_SPEFSCR); in enable_vec()
665 spefscr |= (mfspr(SPR_SPEFSCR) & ~SPEFSCR_FINVS); in spe_handle_fpdata()
Dmachdep_ppc4xx.c125 ccr1 = mfspr(SPR_CCR1); in booke_disable_l2_cache()
/freebsd-12-stable/sys/dev/hwpmc/
Dhwpmc_mpc7xxx.c321 return mfspr(SPR_PMC1); in mpc7xxx_pmcn_read()
324 return mfspr(SPR_PMC2); in mpc7xxx_pmcn_read()
327 return mfspr(SPR_PMC3); in mpc7xxx_pmcn_read()
330 return mfspr(SPR_PMC4); in mpc7xxx_pmcn_read()
333 return mfspr(SPR_PMC5); in mpc7xxx_pmcn_read()
336 return mfspr(SPR_PMC6); in mpc7xxx_pmcn_read()
455 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
460 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
465 pmc_mmcr = mfspr(SPR_MMCR1); in mpc7xxx_start_pmc()
470 pmc_mmcr = mfspr(SPR_MMCR0); in mpc7xxx_start_pmc()
[all …]
Dhwpmc_ppc970.c279 val = mfspr(SPR_970PMC1); in ppc970_pmcn_read()
282 val = mfspr(SPR_970PMC2); in ppc970_pmcn_read()
285 val = mfspr(SPR_970PMC3); in ppc970_pmcn_read()
288 val = mfspr(SPR_970PMC4); in ppc970_pmcn_read()
291 val = mfspr(SPR_970PMC5); in ppc970_pmcn_read()
294 val = mfspr(SPR_970PMC6); in ppc970_pmcn_read()
297 val = mfspr(SPR_970PMC7); in ppc970_pmcn_read()
300 val = mfspr(SPR_970PMC8); in ppc970_pmcn_read()
381 pmc_mmcr = mfspr(SPR_970MMCR0); in ppc970_set_pmc()
391 pmc_mmcr = mfspr(SPR_970MMCR1); in ppc970_set_pmc()
[all …]
/freebsd-12-stable/sys/powerpc/powerpc/
Dcpu.c384 *cps = (mfspr(SPR_PMC1) * 1000) + 4999; in cpu_est_clockrate()
404 *cps = (mfspr(SPR_970PMC1) * 1000) + 4999; in cpu_est_clockrate()
450 hid0 = mfspr(SPR_HID0); in cpu_6xx_setup()
541 hid = mfspr(SPR_HID0); in cpu_6xx_print_cacheinfo()
547 if (mfspr(SPR_L2CR) & L2CR_L2E) { in cpu_6xx_print_cacheinfo()
553 if (mfspr(SPR_L3CR) & L3CR_L3E) in cpu_6xx_print_cacheinfo()
555 mfspr(SPR_L3CR) & L3CR_L3SIZ ? '2' : '1'); in cpu_6xx_print_cacheinfo()
564 switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) { in cpu_6xx_print_cacheinfo()
575 printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT) in cpu_6xx_print_cacheinfo()
577 if (mfspr(SPR_L2CR) & L2CR_L2PE) in cpu_6xx_print_cacheinfo()
[all …]
Dtrap.c305 fscr = mfspr(SPR_FSCR); in trap()
343 mtspr(SPR_DBSR, mfspr(SPR_DBSR)); in trap()
486 (int)mfspr(SPR_MSSSR0), MSSSR_BITMASK); in cpu_printtrap()
494 pa = mfspr(SPR_MCARU); in cpu_printtrap()
495 pa = (pa << 32) | (u_register_t)mfspr(SPR_MCAR); in cpu_printtrap()
497 (int)mfspr(SPR_MCSR), MCSR_BITMASK); in cpu_printtrap()
Dclock.c252 tcr = mfspr(SPR_TCR); in decr_et_start()
282 tcr = mfspr(SPR_TCR); in decr_et_stop()
Dswtch32.S116 mfspr %r3,SPR_SPEFSCR
/freebsd-12-stable/sys/powerpc/include/
Dcpufunc.h150 *tbup = mfspr(TBR_TBU); in mftb()
151 *tblp = mfspr(TBR_TBL); in mftb()
152 } while (*tbup != mfspr(TBR_TBU)); in mftb()
/freebsd-12-stable/sys/powerpc/mpc85xx/
Dmpc85xx.c87 ver = SVR_VER(mfspr(SPR_SVR)); in law_getmax()
233 ver = SVR_VER(mfspr(SPR_SVR)); in law_pci_target()
300 ver = SVR_VER(mfspr(SPR_SVR)); in mpc85xx_enable_l3_cache()
Dplatform_mpc85xx.c322 cpuref->cr_cpuid = mfspr(SPR_PIR); in mpc85xx_smp_get_bsp()
528 mtspr(SPR_DBCR0, mfspr(SPR_DBCR0) | DBCR0_IDM | DBCR0_RST_SYSTEM); in mpc85xx_reset()
Dmpc85xx_gpio.c190 svr = mfspr(SPR_SVR); in mpc85xx_gpio_probe()
/freebsd-12-stable/sys/powerpc/cpufreq/
Ddfs.c177 hid1 = mfspr(SPR_HID1); in dfs_set()
209 hid1 = mfspr(SPR_HID1); in dfs_get()
Dpmcr.c220 pmcr = mfspr(SPR_PMCR); in pmcr_get()
/freebsd-12-stable/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
Dtsan_rtl_ppc64.S102 mfspr r0,256
247 mfspr r0,256

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