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Searched refs:VECREDUCE_ADD (Results 1 – 14 of 14) sorted by relevance

/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
DISDOpcodes.h1233 VECREDUCE_ADD, enumerator
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DLegalizeVectorOps.cpp478 case ISD::VECREDUCE_ADD: in LegalizeOp()
882 case ISD::VECREDUCE_ADD: in Expand()
DSelectionDAGDumper.cpp472 case ISD::VECREDUCE_ADD: return "vecreduce_add"; in getOperationName()
DLegalizeIntegerTypes.cpp211 case ISD::VECREDUCE_ADD: in PromoteIntegerResult()
1554 case ISD::VECREDUCE_ADD: in PromoteIntegerOperand()
2031 case ISD::VECREDUCE_ADD: in PromoteIntOp_VECREDUCE()
2231 case ISD::VECREDUCE_ADD: in ExpandIntegerResult()
DLegalizeVectorTypes.cpp652 case ISD::VECREDUCE_ADD: in ScalarizeVectorOperand()
2219 case ISD::VECREDUCE_ADD: in SplitVectorOperand()
4580 case ISD::VECREDUCE_ADD: in WidenVectorOperand()
DLegalizeDAG.cpp1169 case ISD::VECREDUCE_ADD: in LegalizeOp()
3755 case ISD::VECREDUCE_ADD: in ExpandNode()
DSelectionDAG.cpp379 case ISD::VECREDUCE_ADD: in getVecReduceBaseOpcode()
DSelectionDAGBuilder.cpp9349 Res = DAG.getNode(ISD::VECREDUCE_ADD, dl, VT, Op1); in visitVectorReduce()
DDAGCombiner.cpp1730 case ISD::VECREDUCE_ADD: in visit()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp921 setTargetDAGCombine(ISD::VECREDUCE_ADD); in AArch64TargetLowering()
1078 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1084 setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom); in AArch64TargetLowering()
1182 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in AArch64TargetLowering()
1581 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in addTypeForFixedLengthSVE()
4907 case ISD::VECREDUCE_ADD: in LowerOperation()
10955 (Op.getOpcode() != ISD::VECREDUCE_ADD && in LowerVECREDUCE()
10964 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
10994 case ISD::VECREDUCE_ADD: in LowerVECREDUCE()
12350 return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP); in performVecReduceAddCombineWithUADDLP()
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/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVISelLowering.cpp444 setOperationAction(ISD::VECREDUCE_ADD, MVT::i64, Custom); in RISCVTargetLowering()
534 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in RISCVTargetLowering()
764 setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); in RISCVTargetLowering()
2482 case ISD::VECREDUCE_ADD: in LowerOperation()
3728 case ISD::VECREDUCE_ADD: in getRVVReductionOp()
5346 case ISD::VECREDUCE_ADD: in ReplaceNodeResults()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/CodeGen/
DTargetLoweringBase.cpp853 setOperationAction(ISD::VECREDUCE_ADD, VT, Expand); in initActions()
/freebsd-12-stable/contrib/llvm-project/llvm/include/llvm/Target/
DTargetSelectionDAG.td449 def vecreduce_add : SDNode<"ISD::VECREDUCE_ADD", SDTVecReduce>;
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMISelLowering.cpp288 setOperationAction(ISD::VECREDUCE_ADD, VT, Legal); in addMVEVectorTypes()
994 setTargetDAGCombine(ISD::VECREDUCE_ADD); in ARMTargetLowering()
15974 assert(N->getOpcode() == ISD::VECREDUCE_ADD); in PerformVECREDUCE_ADDCombine()
16210 return DAG.getNode(ISD::VECREDUCE_ADD, dl, ResVT, Ext); in PerformVECREDUCE_ADDCombine()
17736 case ISD::VECREDUCE_ADD: in PerformDAGCombine()