Lines Matching refs:VECREDUCE_ADD

921   setTargetDAGCombine(ISD::VECREDUCE_ADD);  in AArch64TargetLowering()
1078       setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);  in AArch64TargetLowering()
1084     setOperationAction(ISD::VECREDUCE_ADD, MVT::v2i64, Custom);  in AArch64TargetLowering()
1182       setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);  in AArch64TargetLowering()
1581   setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);  in addTypeForFixedLengthSVE()
4907   case ISD::VECREDUCE_ADD:  in LowerOperation()
10955                       (Op.getOpcode() != ISD::VECREDUCE_ADD &&  in LowerVECREDUCE()
10964     case ISD::VECREDUCE_ADD:  in LowerVECREDUCE()
10994   case ISD::VECREDUCE_ADD:  in LowerVECREDUCE()
12350   return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP);  in performVecReduceAddCombineWithUADDLP()
12398   return DAG.getNode(ISD::VECREDUCE_ADD, DL, N->getValueType(0), Dot);  in performVecReduceAddCombine()
16693   case ISD::VECREDUCE_ADD:  in PerformDAGCombine()
17255   case ISD::VECREDUCE_ADD:  in ReplaceNodeResults()