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Searched refs:V0 (Results 1 – 25 of 81) sorted by relevance

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/freebsd-12-stable/contrib/gcc/config/arm/
Dcirrus.md38 "cfadd64%?\\t%V0, %V1, %V2"
48 "cfadd32%?\\t%V0, %V1, %V2"
58 "cfadds%?\\t%V0, %V1, %V2"
68 "cfaddd%?\\t%V0, %V1, %V2"
78 "cfsub64%?\\t%V0, %V1, %V2"
88 "cfsub32%?\\t%V0, %V1, %V2"
98 "cfsubs%?\\t%V0, %V1, %V2"
108 "cfsubd%?\\t%V0, %V1, %V2"
118 "cfmul32%?\\t%V0, %V1, %V2"
128 "cfmul64%?\\t%V0, %V1, %V2"
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp76 Register V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg() local
87 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
89 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
101 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
103 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
116 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
118 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
143 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
144 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
146 .addReg(Mips::V0).addReg(Mips::T9); in initGlobalBaseReg()
DMips16ISelDAGToDAG.cpp75 Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); in initGlobalBaseReg() local
78 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) in initGlobalBaseReg()
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
DMipsRegisterInfo.td89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
123 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
286 V0, V1, A0, A1, A2, A3,
306 V0, V1, A0, A1, A2, A3,
322 V0, V1, A0, A1, A2, A3)>;
330 V0, V1, A0, A1, A2, A3)>;
338 V0, V1,
368 V0, V1, A0, A1, A2, A3,
374 V0, V1, A0, A1, A2, A3,
DMipsCallingConv.td99 // i32 are returned in registers V0, V1, A0, A1, unless the original return
102 CCAssignToReg<[V0, V1, A0, A1]>>>,
269 // except for AT, V0 and T9, are available to be used as argument registers.
315 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
385 CalleeSavedRegs<(add V0, V1, FP,
DMipsBranchExpansion.cpp733 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
735 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
736 .addReg(Mips::V0) in emitGPDisp()
738 MBB.removeLiveIn(Mips::V0); in emitGPDisp()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
DHexagonVectorPrint.cpp74 return (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) || in isVecReg()
81 if (R >= Hexagon::V0 && R <= Hexagon::V31) { in getStringReg()
86 return S[R-Hexagon::V0]; in getStringReg()
183 if (Reg >= Hexagon::V0 && Reg <= Hexagon::V31) { in runOnMachineFunction()
184 LLVM_DEBUG(dbgs() << "adding dump for V" << Reg - Hexagon::V0 << '\n'); in runOnMachineFunction()
188 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2 + 1, in runOnMachineFunction()
190 addAsmInstr(MBB, Hexagon::V0 + (Reg - Hexagon::W0) * 2, in runOnMachineFunction()
DHexagonCallingConv.td116 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
130 CCAssignToReg<[V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15]>>>,
148 CCAssignToReg<[V0]>>>,
156 CCAssignToReg<[V0]>>>,
DHexagonISelDAGToDAG.cpp2164 SDValue V0 = L0.Value; in balanceSubTree() local
2170 if ((RootWeights.count(V0.getNode()) && RootWeights[V0.getNode()] == -2) || in balanceSubTree()
2176 ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0); in balanceSubTree()
2182 std::swap(V0, V1); in balanceSubTree()
2187 assert(NodeHeights.count(V0) && NodeHeights.count(V1) && in balanceSubTree()
2189 int Height = std::max(NodeHeights[V0], NodeHeights[V1]) + 1; in balanceSubTree()
2194 ISD::SHL, SDLoc(V0), VT, V0, in balanceSubTree()
2197 TLI.getScalarShiftAmountTy(DL, V0.getValueType()))); in balanceSubTree()
2199 NewNode = CurDAG->getNode(NOpcode, SDLoc(N), VT, V0, V1); in balanceSubTree()
2222 SDValue V0 = NewRoot.getOperand(0); in balanceSubTree() local
[all …]
/freebsd-12-stable/lib/msun/src/
De_j1f.c96 static const float V0[5] = { variable
147 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1f()
De_j1.c134 static const double V0[5] = { variable
192 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in y1()
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
DVectorCombine.cpp419 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtCmp() local
420 Value *VecCmp = Builder.CreateCmp(Pred, V0, V1); in foldExtExtCmp()
437 Value *V0 = Ext0->getVectorOperand(), *V1 = Ext1->getVectorOperand(); in foldExtExtBinop() local
439 Builder.CreateBinOp(cast<BinaryOperator>(&I)->getOpcode(), V0, V1); in foldExtExtBinop()
463 Value *V0, *V1; in foldExtractExtract() local
465 if (!match(I0, m_ExtractElt(m_Value(V0), m_ConstantInt(C0))) || in foldExtractExtract()
467 V0->getType() != V1->getType()) in foldExtractExtract()
588 Value *V0 = nullptr, *V1 = nullptr; in scalarizeBinopOrCmp() local
590 if (!match(Ins0, m_InsertElt(m_Constant(VecC0), m_Value(V0), in scalarizeBinopOrCmp()
599 bool IsConst0 = !V0; in scalarizeBinopOrCmp()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/VE/
DVECallingConv.td107 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
110 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
128 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
131 CCAssignToReg<[V0, V1, V2, V3, V4, V5, V6, V7]>>,
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/Disassembler/
DRISCVDisassembler.cpp170 MCRegister Reg = RISCV::V0 + RegNo; in DecodeVRRegisterClass()
188 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM2RegisterClass()
208 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM4RegisterClass()
228 RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0, in DecodeVRM8RegisterClass()
242 Reg = RISCV::V0; in decodeVMaskReg()
/freebsd-12-stable/sys/mips/mips/
Dcpu.c81 _ENCODE_INSN(0, T0, T1, V0, OP_DADDU)
93 _ENCODE_INSN(0, T0, T1, V0, OP_ADDU)
100 _ENCODE_INSN(OP_COP0, OP_DMT, V0, 4, 2)
105 _ENCODE_INSN(OP_COP0, OP_MT, V0, 4, 2)
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/Utils/
DLibCallsShrinkWrap.cpp470 Constant *V0 = ConstantFP::get(CI->getContext(), APFloat(0.0f)); in generateCondForPow() local
474 V0 = ConstantExpr::getFPExtend(V0, Exp->getType()); in generateCondForPow()
477 Value *Cond0 = BBBuilder.CreateFCmp(CmpInst::FCMP_OLE, Base, V0); in generateCondForPow()
/freebsd-12-stable/contrib/llvm-project/clang/lib/Driver/ToolChains/
DDarwin.h442 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
445 return TargetVersion < VersionTuple(V0, V1, V2);
452 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
463 : TargetVersion) < VersionTuple(V0, V1, V2);
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp334 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
335 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
336 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
337 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
340 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
341 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
342 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1839 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
1840 SDLoc dl(V0.getNode()); in createGPRPairNode()
1845 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
DInstCombineAddSub.cpp391 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
393 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) { in drillValueDownOneStep()
399 Addend0.set(C, V0); in drillValueDownOneStep()
469 Value *V0 = I->getOperand(0); in simplify() local
471 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) && in simplify()
1849 Value *V0, *V1; in visitSub() local
1850 if (match(Op0, m_AddRdx(V0)) && match(Op1, m_AddRdx(V1)) && in visitSub()
1851 V0->getType() == V1->getType()) { in visitSub()
1854 Value *Sub = Builder.CreateSub(V0, V1); in visitSub()
2386 Value *A0, *A1, *V0, *V1; in visitFSub() local
[all …]
DInstCombineVectorOps.cpp76 Value *V0, *V1; in cheapToScalarize() local
77 if (match(V, m_OneUse(m_BinOp(m_Value(V0), m_Value(V1))))) in cheapToScalarize()
78 if (cheapToScalarize(V0, IsConstantExtractIndex) || in cheapToScalarize()
83 if (match(V, m_OneUse(m_Cmp(UnusedPred, m_Value(V0), m_Value(V1))))) in cheapToScalarize()
84 if (cheapToScalarize(V0, IsConstantExtractIndex) || in cheapToScalarize()
1816 Value *V0 = nullptr, Value *V1 = nullptr) : in BinopElts()
1817 Opcode(Opc), Op0(V0), Op1(V1) {} in BinopElts()
2196 Value *V0 = Shuf.getOperand(0), *V1 = Shuf.getOperand(1); in foldShuffleWithInsert() local
2204 if (NumElts != (int)(cast<FixedVectorType>(V0->getType())->getNumElements())) in foldShuffleWithInsert()
2214 if (match(V0, m_InsertElt(m_Value(X), m_Value(), m_ConstantInt(IdxC)))) { in foldShuffleWithInsert()
[all …]
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoVPseudos.td877 // Mask can be V0~V31
979 // Like VPseudoBinaryMask, but output can be V0.
2213 (mask_type V0),
2218 (mask_type V0), GPR:$vl, sew)>;
2236 (mti.Mask V0),
2241 (mti.Mask V0), GPR:$vl, mti.Log2SEW)>;
2313 (mask_type V0),
2319 (mask_type V0), GPR:$vl, sew)>;
2336 (mask_type V0),
2342 (mask_type V0), GPR:$vl, sew)>;
[all …]
DRISCVRegisterInfo.cpp41 static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
42 static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/RISCV/AsmParser/
DRISCVAsmParser.cpp328 return Kind == KindTy::Register && Reg.RegNum == RISCV::V0; in isV0Reg()
1627 if (RegNo != RISCV::V0) in parseMaskReg()
2401 assert(Inst.getOperand(0).getReg() != RISCV::V0 && in emitVMSGE()
2411 .addReg(RISCV::V0)); in emitVMSGE()
2413 Inst.getOperand(0).getReg() == RISCV::V0) { in emitVMSGE()
2418 assert(Inst.getOperand(0).getReg() == RISCV::V0 && in emitVMSGE()
2420 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
2437 assert(Inst.getOperand(1).getReg() != RISCV::V0 && in emitVMSGE()
2446 .addReg(RISCV::V0) in emitVMSGE()
2451 .addReg(RISCV::V0)); in emitVMSGE()
[all …]
/freebsd-12-stable/sys/mips/include/
Dregnum.h58 #define V0 2 macro
/freebsd-12-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp222 SDValue V0 = N->getOperand(i+1); in tryInlineAsm() local
224 unsigned Reg0 = cast<RegisterSDNode>(V0)->getReg(); in tryInlineAsm()

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